DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
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Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
RSER
LSB
SYSCLK
RSYNC
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
RSIG
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 0, CHANNEL 2
FRAMER 0, CHANNEL 2
3
RSER
RSYNC
RSIG
RSER
RSIG
1
1
2
2
BIT DETAIL
A
B
C/A D/B
A
B C/A D/B
A
B C/A D/B
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
NOTE 1:
4.096MHz BUS CONFIGURATION.
NOTE 2:
8.192MHz BUS CONFIGURATION.
NOTE 3:
RSYNC IS IN THE INPUT MODE (RCR1.5 = 0).