
7.Electrical Interface
© China Daheng Group, Inc. Beijing Image Vision Technology Branch 75
t
d
t
s
t
f
t
r
90%
10%
OUTPUT1
LINE1+
Figure 7-6 Parameter of opto-isolated output circuit
Delay time (td): the response time from OUTPUT1 rises to 50% of amplitude to LINE1+ decreases to
90% of amplitude
Falling time (tf): the response time for LINE1+ to decrease from 90% of the amplitude to 10%
Storage time (ts): the response time from OUTPUT1 decreases to 50% of amplitude to LINE1+ rises
to 10% of amplitude
Rising time (tr): the response time for LINE1+ to rise from 10% of the amplitude to 90%
7.3.3. GPIO 2/3 (Bidirectional) Circuit
1
2
8
7
6
4
5
3
3.3V
Line2
Line3
FPGA INPUT2
FPGA INPUT3
FPGA OUTPUT2
FPGA OUTPUT3
PTC
PTC
Figure 7-7 GPIO 2/3 (bidirectional) circuit