Document Number: 002-10635 Rev. *I
Page
9 of 325
S6J3310/20/30/40 Series
3.
Product Description
3.1
Overview
This chapter explains the product features of S6J3310/20/30/40 series. The description of this chapter should precede the
duplicated description on
Traveo
TM
Platform Hardware Manual
.
3.2
Product Description
The table shows features.
Table 3-1: Product Features
Feature
Description
Technology
40-nm CMOS technology with embedded FLASH
Fully automotive qualified according to ISO/TS 16949 and AEC-Q100
Developed according to ISO26262, safety target ASIL-B
Functional Safety
The product series has some functional safety features suited for ASIL-B application.
Peripherals
See function list.
Power Domain (PD)
See the
Traveo
TM
Platform Hardware Manual
and chapter STATE TRANSITION in detail.
The product series supports the power off control of PD1, PD2 (including PD3 and 5), PD4_0,
PD4_1 and PD6.
The power domain resets of PD3 and PD5 included in PD2 are not supported in the product series,
and "0" is always read from the reset factor flags of them.
This series doesn't support partial wakeup for PD6.
Debug and Trace
See the
Traveo
TM
Platform Hardware Manual
in detail.
−
Standard 5-pin JTAG interface
−
4 kB Embedded Trace Buffer
4-bit trace support for TEQFP package.
System Control
See the
Traveo
TM
Platform Hardware Manual
in detail.
Main and sub oscillator is available.
−
A wide range of 3.6 - 16MHz is available for main oscillator
−
32KHz is available for sub oscillator
Sub clock is enable/disable by register settings
Clock
See the
Traveo
TM
Platform Hardware Manual
in detail.
CLK_CLKO (Clock Output Function) is supported.
Main Oscillation Stabilization Wait Time (at 4 MHz):8.19ms (Initial value)
Embedded CR oscillation
See the
Traveo
TM
Platform Hardware Manual
in detail.
Stabilization time is as followings.
− 0.35 ms to 0.8 ms for 4 MHz (Fast clock)
− 0.43 ms to 1.28 ms for 100 kHz (Slow clock)
Clock Supervisor
See the
Traveo
TM
Platform Hardware Manual
in detail.
This product series doesn’t support clock supervisor output port. (Related register and internal
circuit is implemented.)
Reset
RSTX pin + MD pin simultaneous assert INITX (Same as INITX pin input)
−
Occurrence factor: Simultaneously inputting “L” level to RSTX pin and inputting “L” level to MD
pin
−
Release factor: Inputting “H” level to RSTX pin
See the
Traveo
TM
Platform Hardware Manual
in detail.
Following resets are not mounted on this device.
−
SRSTX (and nSRST pin)
The product series does not support EX5VRST and writing EX5VRSTCNT bits in
SYSC0_SPECFGR
has no effect.