Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 24:Inter-IC Sound (I2S)
928 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.2.
Transmission FIFO Data Register (I2Sn_TXFDAT0 to 15)
These registers are transmission FIFO registers that can maintain up to 66 words (simultaneous transfer
mode) or 132 words (transmission mode only). There are 16 such registers, all consecutively placed in
the register map. This is to support AHB burst transfers. A write access to any of I2Sn_TXFDAT0 to 15
register writes a word of data in the transmission FIFO. Each of these 16 registers are identical in function.
Only one register (i.e. I2Sn_TXFDAT0) is explained here.
Transmission FIFO Data Register 0 (I2Sn_TXFDAT0)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME TXDATA[31] TXDATA[30] TXDATA[29] TXDATA[28] TXDATA[27] TXDATA[26] TXDATA[25] TXDATA[24]
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME TXDATA[23] TXDATA[22] TXDATA[21] TXDATA[20] TXDATA[19] TXDATA[18] TXDATA[17] TXDATA[16]
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME TXDATA[15] TXDATA[14] TXDATA[13] TXDATA[12] TXDATA[11] TXDATA[10] TXDATA[9] TXDATA[8]
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME TXDATA[7] TXDATA[6] TXDATA[5] TXDATA[4] TXDATA[3] TXDATA[2] TXDATA[1] TXDATA[0]
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] TXDATA : Transmit Data
Word to be transmitted can be written as long as transmission FIFO is not full.
Write access can be performed regardless of shift register's operation status. Write access to full
transmission FIFO is ignored and I2Sn_STATUS:TXOVR flag is set. Although writing data is accessed
in word, half-word, and byte access, actual number of bits to be transmitted is determined by
I2Sn_MCR0REG:S0WDL and I2Sn_MCR0REG:S1WDL (when frame is 2 sub frame).
The data read from I2Sn_TXFDAT0 returns "0".