Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 23:Stereo Audio DAC
880 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.
Operation
This section describes how to use the Stereo Audio DAC
The Stereo Audio DAC is configured to be used at a sampling frequency of 8-48KHz, an oversampling
rate of 64-512, and an operating frequency of 256fs or 512fs.
3.1.
Initialization
Reset operation : reset the Stereo Audio DAC after powering up
DMA Interface Unused:
The sequence for powering up the analog DAC is as follows.
1) Configure the OSR and DACCLK bit of the DAOSR register.
2) Write a "1" into the INIT bit and DAE bit of the DACR register. This will release the power down
state of the analog DAC and allow it to power up.
3) Wait for at least 300 sampling cycles (1/fs) before proceeding to the next step (step 4)
4) Write a "0" into the INIT bit of the DACR register. This will enable the output data pins of the
digital interface thus providing data to the analog DAC.
5) Configure the PCL/PCR bit of the DPCR register.
6) Configure the FEST bit of the DACTRL register.
7) Writing the 0x7 into the INTREN register if you want to use DATA_REQ_IRQ, UDRN_IRQ, the
OVFL_IRQ. As a result, DATA_REQ_IRQ is asserted.
DMA Interface Used:
The sequence for powering up the analog DAC is as follows.
1) Configure the OSR and DACCLK bit of the DAOSR register.
2) Write a "1" into the INIT bit and DAE bit of the DACR register. This will release the power down
state of the analog DAC and allow it to power up.
3) Wait for at least 300 sampling cycles (1/fs) before proceeding to the next step (step 4)
4) Write a "0" into the INIT bit of the DACR register. This will enable the output data pins of the
digital interface thus providing data to the analog DAC.
5) Configure the PCL/PCR bit of the DPCR register.
6) Configure the FEST bit of the DACTRL register. Write a "1" into the DMAEN bit of the DACTRL
register. As a result, DAC_DMA_REQ is asserted.
7) Writing the 0xF into the INTREN register if you want to use DMA_ERR_IRQ, DATA_REQ_IRQ,
UDRN_IRQ, OVFL_IRQ. As a result, DATA_REQ_IRQ is asserted.
Note;
−
The write access to DAOSR/DACR register is effective at DABUSY_DABUSY=0. Write access to
DAOSR / DACR register is discarded in the case of DABUSY_DABUSY=1.
−
The data output pins of the analog DAC may take up to 715ms to stabilize after the DAE bit has
been set
−
The Stereo Audio DAC will generate a pop noise when a transition from high-to-low or low-to-high
occurs on the DAE bit of the DACR register during power up or power down. Add external
circuitry to suppress such pop noises if necessary.
−
Do not change the DPCR register dynamically.