Cypress S6J3110 Series, Как пользоваться инструкцией, Страница: 21 / 27

How to Use A/D Converter for S6J3110/ S6J3120 Series
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Document No. 002-04457 Rev. *B 21
4.4 A/D Activation Trigger Control Status Register (ADTCS)
The A/D Activation Trigger Control Status Register (ADTCS) is used for A/D activation request confirmation,
permission/prohibition of interrupt request, confirmation of interrupt request status, selection of activation factor,
selection of conversion mode, control of protection function, selection of the compare value used for compare
operation, buffer control of the compare value and selection of an analog input channel.
Table 6. A/D Activation Trigger Control Status Register Example of Settings
Bit Bit name Description
Setting register
Value Contents
15 BUSY A/D activation Request in Progress Bit 0
A/D activation has not been
requested
14 INT Interrupt Request Flag Bit 0
A/D conversion has not been
completed
13 INTE Interrupt Request Enable Bit 1 Enable interrupt request output.
12-11 STS[1-0] A/D activation Factor Selection Bits 0 Software activation
10 RPT Repeat Conversion Selection Bit 1 Repeat conversion
9 PRT A/D Data Register Protection Enable Bit 0 Protection disabled
8 PRTS
A/D Data Register Protection Release Selection
Bit
0
Data reading and interrupt flag
clear
7-6 SEL[1-0] Count Direction Selection Bits 0 Both up/down count
5 BUFX Compare Register Buffer Function Control Bit 1 Disabled
4 BTS Compare Register Buffer Transfer Control Bit 0
When the
“
BUFX” is disabled,
this bit is disabling.
3-0 Reserved Reserved 0
－
Note:
-BUSY, INT, PRTS, SEL, BUFX, BTS bits are initial values in this APPLICATION NOTE.
4.5 A/D Activation Trigger Control Status Clear Register (ADTCSC)
The A/D Activation Trigger Control Status Clear Register (ADTCSC) clears the bits in the A/D activation trigger
control status register (ADTCS).
Table 7. A/D Activation Trigger Control Status Clear Register Example of Settings
Bit Bit name Description
Setting register
Value Contents
15 BUSYC BUSY Clear Bit 1
Clear the ADTCS
Register BUSY bit.
14 INTC INT Clear Bit 1
Clear the ADTCS
Register INT bit.
13-0
Reserved Reserved
0
－