Cypress S6J3110 Series, Как пользоваться инструкцией, Страница: 20 / 27

How to Use A/D Converter for S6J3110/ S6J3120 Series
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Document No. 002-04457 Rev. *B 20
4 Registers
This section shows the registers of the A/D converter in the example of settings.
4.1 Analog Input Control Register (ADER)
The Analog Input Control Register (ADER) control analog input. This register is target of the Key Code Register.
(Please refer to the "4.1.1.Key Code Register" of the
“CHAPTER: 12 Bit-A/D Converter” in the S6J3110 / S6J3120
Series Hardware Manual.)
Table 3. Analog Input Control Register Example of Settings
Bit Bit name Description
Setting register
Value Contents
31-0 ADE[31-0] Analog Input Enable Bits 1 (*) Enable
Note:
*
When an Analog input selects AN14, Analog Input Enable Bit is
“ADE14=1” setting.
4.2 A/D Mode Setting Register (ADMD)
The A/D Mode Setting Register (ADMD) sets the function of setting the compare time and sampling time for A/D
conversion.
Table 4. A/D Mode Setting Register Example of Settings
Bit Bit name Description
Setting register
Value Contents
7 STPCEN Sampling Time Setting per Channel Enable Bit 0
Sampling time
setting common to all
channels
6-4 Reserved Reserved 0
－
3-2
CT[1-0] Compare Time Setting Bits
0
28 peripheral clock
cycles
1-0 ST[1-0] Sampling Time Setting Bits 3
48 peripheral clock
cycles
4.3 A/D Activation Trigger Extended Control Register (ADTECS)
The A/D Activation Trigger Extended Control Register (ADTECS) selects the activation factor and analog Input
channel.
Table 5. A/D Activation Trigger Extended Control Register Example of Settings
Bit Bit name Description
Setting register
Value Contents
15-9 Reserved Reserved 0
－
8 STS2 A/D activation Factor Selection Bits 0 Software activation
7-5
Reserved Reserved
0
－
4-0 CHSEL[4-0] Analog Channel Selection Bits 14 Channel 14