S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D
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1.3.6.3 Access to the DualFlash area
The following two access modes are available for accessing the DualFlash area from the CPU.
CPU ROM mode
CPU programming mode
These modes can be selected by the dual flash access size bits (DFASZR:DASZ).
CPU ROM Mode
This mode only allows reading of flash memory data.
This mode is entered by setting the dual flash access size bits (DFASZR:DASZ) to "0b10" (32-bit read), and enables word
access.
However, in this mode, it is not possible to execute commands, to activate the automatic algorithm or to write or erase
data.
The flash memory always enters this mode after reset is released.
CPU Programming Mode
This mode allows reading, writing, and erasing of data.
This mode is entered by setting the dual flash access size bits (DFASZR: DASZ) to "0b01" (16-bit read/write), and enables
flash programming.
Because word access is not possible in this mode, programs that are contained in the DualFlash area cannot be executed.
The operation while in this mode is as follows.
During reading
Flash memory is accessed in half-words, with data read out in blocks of 16 bits.
During writing commands
The automatic algorithm can be activated to write or erase data. See Section "
" for details on
the automatic algorithm.
Table 1-7 Access Modes of Flash Memory
Access Mode
Access Size
Automatic
Algorithm
Instruction Execution in the
DualFlash Area
CPU ROM mode
32-bit
disable
enable
CPU programming mode
16-bit
enable
Prohibited
Flash Accelerator/Sync Down/Interrupt/ECC ERR Address Capture functions are not equipped in the DualFlash area.
Set the Dual Flash Read Wait Cycle bit (DFRWTR : DRWT) for the access method to the DualFlash area.
