Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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20 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Pin Information
1.1.2 CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI, CY8CTST200-24LQXI,
CY8CTST200A-24LQXI PSoC 24-Pin Part Pinout
Table 1-2. 24-Pin QFN Part Pinout **
Pin
No.
Type
Name Description
CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI,
CY8CTST200-24LQXI, CY8CTST200-24LQXI
PSoC Device
Digital Analog
1 IO I P2[5] XTAL Out
2 IO I P2[3] XTAL In
3 IO I P2[1]
4 IOHR I P1[7] I2C SCL, SPI SS
5 IOHR I P1[5] I2C SDA, SPI MISO
6 IOHR I P1[3] SPI CLK
7 IOHR I P1[1] TC CLK*, I2C SCL, SPI MOSI
8 NC No connection
9 Power Vss Ground pin
10 IOHR I P1[0] TC DATA*, I2C SDA, SPI CLK
11 IOHR I P1[2]
12 IOHR I P1[4] EXTCLK
13 IOHR I P1[6]
14 Input XRES Active high external reset with internal pull down
15 IO I P2[0]
16 IOH I P0[0]
17 IOH I P0[2]
18 IOH I P0[4]
19 IOH I P0[6]
20 Power Vdd Power pin
21 IOH I P0[7]
22 IOH I P0[5]
23 IOH I P0[3] Integrating input
24 IOH I P0[1] Integrating input
LEGEND A = Analog, I = Input, O = Output, H = 5 mA High Output Drive, R = Regulated Output Option.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not con-
nected to ground, it must be electrically floated and not connected to any other signal.
QFN
(Top View)
P2[5]
P1[7]
P1[5]
P1[3]
1
2
3
4
5
6
18
17
16
15
14
13
P0[2]
P0[0]
24 23 22 21 20 19
P0
[3
]
P0
[5
]
P0
[7
]
Vd
d
P0[4]
7 8
9
10 11 12
P1
[1
]
P1
[0
]
P1
[2
]
P2[3]
P2[1]
NC
P1[6]
P1
[4
]
XRES
P2[0]
P0
[6
]
P0
[1
]
Vs
s
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