Cypress PSoC CY8C23533, Техническое справочное руководство

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32 Document # 001-20559 Rev. *D
Section B: PSoC Core
Core Register Summary
The table below lists all the PSoC registers for the CPU core in address order within their system resource configuration. The
bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’. For the
core registers, the first ‘x’ in some
register addresses represents either bank 0 or bank 1. These registers are listed through-
out this manual in bank 0, even though they are also available in bank 1.
The CY8C24533, CY8C23533, CY8C23433CY8C24633 PSoC devices have 1 digital row and 2 analog columns.
Summary Table of the Core Registers
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
M8C REGISTER (page
44
)
x,F7h CPU_F PgMode[1:0] XIO Carry Zero GIE RL : 02
SUPERVISORY ROM (SROM) REGISTERS (page
51
)
x,FEh CPU_SC
R1 IRESS SLIMO ECO EXW ECO EX IRAMDIS # : 00
1,FAh FLS_PR1 Bank[1:0] RW:00
RAM PAGING (SRAM) REGISTERS (page
58
)
x,6Ch TMP_DR
0 Data[7:0] RW : 00
x,6Dh TMP_DR
1 Data[7:0] RW : 00
x,6Eh TMP_DR
2 Data[7:0] RW : 00
x,6Fh TMP_DR
3 Data[7:0] RW : 00
x,F7h CPU_F PgMode[1:0] XIO Carry Zero GIE RL : 02
INTERRUPT CONTROLLER REGISTERS (page
64
)
0,DAh INT_CLR
0 VC3 Sleep GPIO SAR8 ADC Analog 1 Analog 0 V Monitor RW : 00
0,DBh INT_CLR
1 DCB03 DCB02 DBB01 DBB00 RW : 00
0,DDh INT_CLR
3 I2C RW : 00
0,DEh INT_MSK
3 ENSWINT I2C RW : 00
0,E0h INT_MSK
0 VC3 Sleep GPIO SAR8 ADC Analog 1 Analog 0 V Monitor RW : 00
0,E1h INT_MSK
1 DCB03 DCB02 DBB01 DBB00 RW : 00
0,E2h INT_VC Pending Interrupt[7:0] RC : 00
x,F7h CPU_F PgMode[1:0] XIO Carry Zero GIE RL : 02
GENERAL PURPOSE IO (GPIO) REGISTERS (page
8
)
0,00h PRT0DR Data[7:0] RW : 00
0,01h PRT0IE Interrupt Enables[7:0] RW : 00
0,02h PRT0GS Global Select[7:0] RW : 00
0,03h PRT0DM
2 Drive Mode 2[7:0] RW : FF
1,00h PRT0DM
0 Drive Mode 0[7:0] RW : 00