Cypress PSoC CY8C23533, Техническое справочное руководство

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226 Document # 001-20559 Rev. *D
Analog Interface
18.3.1.3 SAR Timing
Another important function of the SAR hardware is to syn-
chronize the IO read (the point at which the comparator
value is used to make the SAR decision) to when the analog
comparator bus is valid. Under normal conditions, this point
is at the rising edge of PHI1 for the previous compute cycle.
When the OR instruction is executed in the CPU, a few CPU
clocks cycle into the instruction and an IOR signal is
asserted to initiate a read of the DAC register. The SAR
hardware then stalls the CPU clock, for one 24 MHz clock
cycle after the rising edge of PHI1. When the stall is
released, the IO read completes and is immediately followed
by an IO write. In this sequence of events, the DAC register
is written with the new value within a few CPU clocks after
PHI1. The rising edge of PHI1 is also the optimal time to write the
DAC register for maximum settling time. The timing from the
positive edge of PHI1 to the start of the IO write is 4.5
clocks, which at 24 MHz is 189 ns. If the analog clock is run-
ning at 1 MHz, this allows over 300 ns for the DAC output
and comparator to settle.
Figure 18-7. General SAR Timing
PHI1
PHI2
ACMP
IOR
IOW
STALL
Comparator is valid on PHI1 rising.
SAR computation is done and IOR
finishes. DAC output is valid at
end of PHI2.
Comparator is now valid for
previous IOW, repeat process.
IOR causes STALL to
assert, to wait for PHI1
rising. New value is written to
DAC register.