Cypress EX-USB FX3, Руководство программиста

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44 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Overview
The boot loader is also responsible for restoring the state of FX3 when the device transitions back
from a low power mode to the normal active power mode. The process of system restoration is
called 'Warm boot'.
3.10 Clocking
Clocks in FX3 are generated from a single 19.2 MHz (±100 ppm) crystal oscillator. It is used as the
source clock for the PLL, which generates a master clock at frequencies up to up to 500 MHz. Four
system clocks are obtained by dividing the master clock by 1, 2, 4, and 16. The system clocks are
then used to generate clocks for most peripherals in the device through respective clock select and
divide (CSD) block A CSD block is used to select one of the four system clocks and then divide it
using the specified divider value. The depth and accuracy of the divider is different for different
peripherals,
Figure 3-17. CSD
The CPU clock is derived by selecting and dividing one of the four system clocks by an integer factor
anywhere between 1 and 16. The bus clocks are derived from the CPU clock. Independent 4-bit
dividers are provided for both the DMA and MMIO bus clocks. The frequency of the MMIO clock,
however, must be an integer divide of the DMA clock frequency.
A 32 kHz external clock source is used for low-power operation during standby. In the absence of a
32 kHz input clock source, the application can derive this from the reference clock produced by the
oscillator.
Certain peripherals deviate from the general clock derivation strategy. The fast clock source of GPIO
is derived from the system clocks using a CSD. The core clock is a fixed division of the fast clock.
The slow clock source of GPIO is obtained directly from the reference clock using a programmable
divider. The standby clock is used to implement 'Wake-Up' on GPIO. The I2S block can be run off an
internal clock derived from the system clocks or from an external clock sourced through the
I2S_MCLK pin of the device.
Exceptions to the general clock derivation strategy are blocks that contain their own PLL, because
they include a PHY that provides its clock reference. For example, the UIB block derives its
'epm_clk', 'sie_clk', 'pclk', and 'hd3_clk' using the standby clock, dma-bus clock, 30/120 MHz clock
from the USB2 PHY and a 125 MHz clock from the USB3PHY. The sie_clk runs the USB 2.0 logic
blocks while USB 3.0 logic blocks are run using the pclk. The hd3_clk runs certain host and USB 3.0
logic blocks while the epm_clk runs the end point manager.
%
CLKIN CLKOUT
PLL_SYS_CLK_16
PLL_SYS_CLK_4
PLL_SYS_CLK_2
PLL_SYS_CLK_1
DIVIDE
PERIPHERAL_CLK
4:1
MUX
CLOCK SELECT AND DIVIDE BLOCK
PLL_SYS_
CLKS[3:0]
PLL_SYS_
CLK_SEL
SEL_CLK
_DIV[N:0]
DIV_CLK
_OUT
CSD