Cypress EX-USB FX3, Руководство программиста

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138 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 P-Port Register Access
10.2.12 PP_RD_MAILBOX
P-Port Read (Egress) Mailbox Registers. These registers contain a message of up to 8 bytes from
firmware to the Application Processor. The semantics of the possible messages will be defined as
part of the software specification. These registers also appear in the P-Port MMIO space as
PIB_RD_MAILBOX*. When firmware writes data into the high word of PIB_RD_MAILBOX the event
PP_EVENT.RD_MB_FULL is set. The expected action is that the Application Processor reads the
message and interprets it and then clears PP_EVENT.RD_MB_FULL, which sets
PIB_INTR.RD_MB_EMPTY to signal firmware for the next message (if needed).
10.2.13 PP_SOCK_STAT
P-Port Socket Status Register. These registers contain one bit for each of the 32 sockets in the P-
port, indicating the buffer availability of each socket.
10.3 INTR and DRQ signaling
INTR signal is derived by a bitwise OR of (PP_EVENT & PP_INTR_MASK) registers. This allows AP
to selectively program PP_INTR_MASK for desired exception and socket events.
Typically, status bit DMA_WMARK_EV or DMA_READY_EV is made available as a DRQ signal by
configuring PP_DRQR5_MASK. It is possible to combine DMA_READY or DMA_WMARK with a
handshake DACK signal from AP, if required. This is done using a programmable GPIF state
machine. For the rest of this document use of DACK is not considered.
The polarity of both DRQ and INTR signals is configurable.
11 DMA_WMARK_EV RW R 0
Usage of DMA_WMARK is explained in PAS.
0: P-Port has fewer than <watermark> words
left (can be 0)
1: P-Port is ready for transfer and at least
<watermark> words remain
12 DMA_READY_EV RW R 0
Usage of DMA_READY is explained in PAS.
0: P-port not ready for data transfer
1: P-port ready for data transfer
13 RD_MB_FULL W1S RW1C 0 1: RD Mailbox is full - message must be read
14 WR_MB_EMPTY RW RW1C 1
1: WR Mailbox is empty - message can be writ-
ten
This field is cleared by PIB when message is
written to MBX, but can also be cleared by AP
when used as interrupt. This field is set by PIB
only once when MBX is emptied by firmware.
15 WAKEUP W1S RW1C 0
0: No wakeup event
1: Bay returned from standby mode, signal
must be cleared by software
Bits Name HW SW Default Description
63:0 RD_MAILBOX RW R 0 Read mailbox message to AP
Bits Name HW SW Default Description
31:0 SOCK_STAT W R 0
For socket <x>, bit <x> indicates:
0: Socket has no active descriptor or descriptor is
not available (empty for write, occupied for read)
1: Socket is available for reading or writing
Bits Name HW SW Default Description