Cypress EX-USB FX3, Руководство программиста

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FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 137
FX3 P-Port Register Access
10.2.9 PP_DMA_SIZE
P-Port DMA Transfer Size Register. This register indicates the (remaining) size of the transfer. This
register is initialized to the number of bytes available in the buffer for egress transfers and the size of
the buffer for ingress transfers. This register can be modified by the AP for shorter ingress transfers.
The value read from this register is not valid unless DMA_XFER.SIZE_VALID is true.
10.2.10 PP_WR_MAILBOX
P-Port Write (Ingress) Mailbox Registers. These registers contain a message of up to 8 bytes from
the Application Processor to firmware. The semantics of the possible messages is defined as part of
the software specification. These registers also appear in the P-Port MMIO space as
PIB_WR_MAILBOX. When the Application Processor writes data into the high word of
PP_WR_MAILBOX the interrupt PIB_INTR.WR_MB_FULL is set. The expected action is that firm-
ware reads the message and then clears PIB_INTR.WR_MB_FULL, which will set
PP_EVENT.WR_MB_EMPTY to signal AP for the next message (if needed).
10.2.11 PP_EVENT
P-Port Event Register. This register indicates all types of events that can cause INTR or DRQ to
assert.
Bits Name HW SW Default Description
15:0 DMA_SIZE RW RW 0
Size of DMA transfer. Number of bytes
available for read/write when read, num-
ber of bytes to be read/written when writ-
ten.
Bits Name HW SW Default Description
63:0 WR_MAILBOX R RW 0 Write mailbox message from AP
Bits Name HW SW Default Description
0 SOCK_AGG_AL RW R 0
0 : SOCK_STAT_A[7:0] is all zeroes
1: At least one bit set in SOCK_STAT_A[7:0]
1 SOCK_AGG_AH RW R 0
0 : SOCK_STAT_A[15:8] is all zeroes
1: At least one bit set in SOCK_STAT_A[15:8]
2 SOCK_AGG_BL RW R 0
0 : SOCK_STAT_B[7:0] is all zeroes
1: At least one bit set in SOCK_STAT_B[7:0]
3 SOCK_AGG_BH RW R 0
0 : SOCK_STAT_B[15:8] is all zeroes
1: At least one bit set in SOCK_STAT_B[15:8]
4 GPIF_INT W1S RW1C 0 1: State machine raised host interrupt
5 PIB_ERR W1S RW1C 0
The socket based link controller encountered
an error and needs attention. FW clears this bit
after handling the error. The error code is indi-
cated in PP_ERROR.PIB_ERR_CODE
6 MMC_ERR W1S RW1C 0
An unrecoverable error occurred in the PMMC
controller. FW clears this bit after handling the
eror. The error code is indicated in
PP_ERROR.MMC_ERR_CODE
7 GPIF_ERR W1S RW1C 0
An error occurred in the GPIF. FW clears this
bit after handling the error. The error code is
indicated in PP_ERROR.GPIF_ERR_CODE