enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
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SPI
18.1.1.1
SPI Protocol Signal Definitions
The SPI protocol signal definitions are located in
The use of the SS_ signal varies according to the capability
of the slave device.
18.1.2
SPI Master Function
The SPI Master (SPIM) offers SPI operating modes 0-3. By
default, the most significant bit (MSb) of the data byte is
shifted out first. An additional option can be set to reverse
the direction and shift the data byte out the least significant
bit (LSb) first. (Refer to the timing diagrams for this function
on page
When configured for SPIM, DR0 functions as a Shift register
with input from the DATA input (MISO) and output to the pri-
mary output F1 (MOSI). DR1 is the TX Buffer register and
DR2 is the RX Buffer register.
The SPI protocol requires data to be registered at the device
input, on the opposite edge of the clock that operates the
output shifter. An additional register (RXD), at the input to
the DR0 Shift register, has been implemented for this pur-
pose. This register stores received data for one-half cycle
before it is clocked into the Shift register.
The SPIM controls data transmission between master and
slave because it generates the bit clock for internal clocking
and for clocking the SPIS. The bit clock is derived from the
CLK input selection.
There are four control bits and four status bits in the Control
register (SPI_CR) that provide for enCoRe V device inter-
facing and synchronization.
The SPIM hardware has no support for driving the Slave
Select (SS_) signal. The behavior and use of this signal is
application and enCoRe V device dependent and, if
required, must be implemented in firmware.
18.1.2.1
Usability Exceptions
The following are usability exceptions for the SPI Protocol
function.
■
The SPI_RXR (RX Buffer) register is not writeable.
■
The SPI_TXR (TX Buffer) register is not readable.
18.1.2.2
Block Interrupt
The SPIM block has a selection of two interrupt sources:
interrupt on TX Reg Empty (default) or interrupt on SPI
Complete. Mode bit 1 in the Function register controls the
selection. These modes are discussed in detail in
.
If SPI Complete is selected as the block interrupt, the Con-
trol register must be read in the interrupt routine so that this
status bit is cleared; otherwise, no subsequent interrupts are
generated.
18.1.3
SPI Slave Function
The SPI Slave (SPIS) offers SPI operating modes 0-3. By
default, the MSb of the data byte is shifted out first. An addi-
tional option can be set to reverse the direction and shift the
data byte out LSb first. (Refer to the timing diagrams for this
function on page
.)
The SPI protocol requires data to be registered at the device
input, on the opposite edge of the clock that operates the
output shifter. An additional register (RXD), at the input to
the DR0 Shift register, is implemented for this purpose. This
register stores received data for one-half cycle before it is
clocked into the Shift register.
The SPIS function derives all clocking from the SCLK input
(typically an external SPI Master). This means that the mas-
ter must initiate all transmissions. For example, to read a
byte from the SPIS, the master must send a byte.
There are four control bits and four status bits in the Control
register (SPI_CR) that provide for enCoRe V device inter-
facing and synchronization.
There is an additional data input in the SPIS, Slave Select
(SS_), which is an active low signal. SS_ must be asserted
to enable the SPIS to receive and transmit. SS_ has two
high level functions: 1) To allow the selection of a given
slave in a multi-slave environment, and 2) To provide addi-
tional clocking for TX data queuing in SPI modes 0 and 1.
SS_ may be controlled from an external pin or can be con-
trolled by way of user firmware.
When SS_ is negated, the SPIS ignores any MOSI/SCLK
input from the master. In addition, the SPIS state machine is
reset and the MISO output is forced to idle at logic 1. This
allows for a wired-AND connection in a multi-slave environ-
ment. Note that if High-Z output is required when the slave
is not selected, this behavior must be implemented in firm-
ware with I/O writes to the Port Drive register.
18.1.3.1
Usability Exceptions
The following are usability exceptions for the SPI Slave
function.
■
The SPI_RXR (RX Buffer) register is not writeable.
■
The SPI_TXR (TX Buffer) register is not readable.
Table 18-1. SPI Protocol Signal Definitions
Name
Function
Description
MOSI
Master Out
Slave In
Master data output.
MISO
Master In
Slave Out
Slave data output.
SCLK
Serial Clock Clock generated by the master.
SS_
Slave Select
(Active Low)
This signal is provided to enable multi-slave con-
nections to the MISO pin. The MOSI and SCLK pins
can be connected to multiple slaves, and the SS_
input selects which slave receives the input data
and drives the MISO line.
