CY8CPROTO-064B0S3 PSoC 64 "Secure Boot" Prototyping Kit Guide, Doc. # 002-29505 Rev. *B
37
Hardware
5.2.5
Expansion Connectors
5.2.5.1
Functionality of the J1 and J2 Headers (Target Board)
The target PSoC 64 section contains two single inline headers (J1 and J2). These 1×21-pin headers
have 0.1-inch spacing and include a subset of the GPIOs available on the PSoC 64 device.
Figure 5-6. J1 and J2 Headers
PSoC 64 section
KitProg3
KitProg3
USB connector (J8)
PSoC 64 SWD/JTAG
programming headers
(J7,J5)
GND
VIN
P7_0
P7_1
P7_2
P7_3
P0_2
P0_3
P6_3
GND
P10_0
P10_1
P10_2
P10_3
P10_4
P10_5
P8_0
P8_1
VREF
GND
VDDUSB
GND
P6_VDD
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
GND
P9_0
P9_1
P9_2
P9_3
P5_6
P5_7
P0_5
P0_4
VCC_FLASH
GND
VBACKUP
PSoC 64 I/O (J2)
PSoC 64 I/O (J1)