Low-Power Design Considerations
CY8C20xx7/S CapSense
®
Design Guide
Doc. No. 001-78329 Rev. *E
68
8.1.6 Global Interrupt Enable
The Global Interrupt Enable register (CPU_F) need not be enabled to wake the CapSense controller from interrupts.
The only requirement to wake up from sleep by an interrupt is to use the correct interrupt mask within the INT_MSKx
registers, as in the following example. If global interrupts are disabled, the ISR that wakes the CapSense controller is
not executed but the CapSense controller still exits sleep mode.
In this case, you must manually clear the pending interrupt or enable global interrupts to allow the ISR to be serviced.
Interrupts are cleared within the INT_CLRx registers.
//Set Mask for GPIO Interrupts
M8C_EnableIntMask(INT_MSK0, INT_MSK0_GPIO)
// Clear Pending GPIO Interrupt
INT_CLR0 &= 0x20;
8.2 Post Wakeup Execution Sequence
If the CapSense controller is awakened through a reset, execution starts at the beginning of the boot code. If the
CapSense controller is awakened by an interrupt service routine, the first instruction to execute is the one
immediately following the sleep instruction. This is because the instruction immediately following the sleep instruction
is pre-fetched before the CapSense controller is fully asleep. Therefore, if global interrupts are disabled, the
instruction execution will continue where it left off before sleep was initiated.
8.2.1 PLL Mode Enabled
If PLL mode is enabled, the CPU frequency must be reduced to the minimum of 3 MHz before going to sleep. This is
because the PLL always overshoots as it attempts to relock after the CapSense controller wakes up and is re-
enabled. Additionally, you should wait 10 ms after wakeup before normal CPU operation begins to ensure proper
execution. This implies that, to use sleep mode and the PLL, the software must be able to execute at 3 MHz. A
simple write to the OSC_CR0 register can reduce CPU speed. However, this register just sets a divider of SYSCLK,
which means that the CPU speed will vary between part families with different SYSCLKs. Typically, SYSCLK is
24 MHz
OSC_CR0 &= 0xf8; // CPU = 3 Mhz IMO = 24 Mhz
8.2.2 Execution of Global Interrupt Enable
Avoid interrupts on the instruction boundary of writing the SLEEP bit. This can cause all firmware preparations for
going to sleep to be bypassed, if a sleep command is executed on a return from interrupt (reti) instruction. To prevent
this, interrupts are temporarily disabled before sleep preparations and then re-enabled before going to sleep.
Because of the timing of the Global Interrupt instruction, an interrupt cannot occur during the next instruction, which in
this case is setting the SLEEP bit.
8.2.3 Recommended I
2
C Slave Implementation in Sleep Mode
When I
2
C is used in sleep mode, certain implementation guidelines must be followed to keep the I
2
C bus from locking
or corrupted transactions from occurring.
8.2.3.1 Wakeup from I
2
C Sleep Mode using HW Address Match
To enable the wakeup through I
2
C, set the HW Addr EN bit so that the I
2
C slave block wakes the system if and only if
the address matches. The I
2
C block responds to the transactions on the I
2
C bus when the system is in sleep mode
but when the system is in sleep mode, the system clock shuts down.
Therefore, if the I
2
C block must respond to the transactions on the I
2
C bus, then the block does not have system
clock to work on. As a result, the incoming SCL clock is used as the clock for the block to respond to the transactions
on the bus.
When the address matches, the behavior depends on the CLK_STRETCH_EN setting. If this bit is set high, SCL is
pulled low until the IMO is operational. If this bit is set low, the slave NACKS all I
2
C transactions addressed to it until
the CPU wakes up and sets the ACK bit. When clock stretch mode is disabled, after a wakeup IRQ, any other start
condition will not be recognized by the device until the IMO is operational. All transactions in this duration will receive
a NACK.
depicts the wakeup sequence through I
2
C.