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CY8C20xx7/S CapSense
®
Design Guide
Doc. No. 001-78329 Rev. *E
66
8. Low-Power Design Considerations
Power consumption is an important aspect of microcontroller designs. Among the several techniques to reduce the
average current used by the CapSense controller, sleep mode is the most popular. The CapSense controller uses
sleep mode when it is not required to perform any function, similar to a cell phone backlight dimming after an idle
period. This is done to reduce the average current consumed by the device, a necessity of all battery applications.
The CapSense controller enters sleep mode by writing a
„1‟ to the SLEEP bit within the CPU_SCR0 register (Bit 3).
This is accomplished by calling the M8C_Sleep macro.
While in sleep mode:
the central CPU is stopped
the IMO is disabled
the bandgap voltage reference is powered down
the flash memory model is disabled
The only circuits left in operation are the supply voltage monitor and the 32-kHz internal oscillator.
Power-saving techniques other than the standard sleep mode are:
I
2
C sleep mode (see section
Disable CapSense (PSoC) analog block references
Disable CT and SC blocks
Disable CapSense (PSoC) analog output buffers
Set drive modes to analog HI-Z
Sleep mode has negative effects for a design. If not used carefully, it can cause an unpredictable operation. The
PSoC must be correctly awakened from sleep when necessary and the user must be aware that the device is
sleeping to allow extra processing.
8.1 Additional Power Saving Techniques
All of the power-saving techniques, with the exception of sleep mode, is application-based. Some of them produce
undesirable results. Each technique is discussed in detail in the following sections.
8.1.1 Set Drive Modes to Analog HI-Z
The state of the CapSense controller drive modes can affect power consumption. You can change the drive modes
only on pins that do not cause adverse effects to the system. The change must occur in a sequence that does not
produce line glitches. This sequence depends on the current drive mode of the pin and the state of the port data
register. With the CapSense controller drive mode structure, the pin must temporarily be in either Resistive Pull-up or
Resistive Pull-down drive mode when switching between HI-Z or Strong drive modes. The temporary drive mode is
the opposite of the previous value on the pin. Therefore, if the pin was driven high, then the temporary drive mode
must be Resistive Pull-down. This ensures that the drive mode of the pin is not resistive, which eliminates any
possible glitch.
The drive modes are set manually in software, before going to sleep. Three registers, PRTxDM0, PRTxDM1, and
PRTxDM2, control the drive modes. One bit per register is assigned to a pin. Therefore, to change the drive mode of
a single pin, three register writes are needed. However, this is convenient because an entire port is changed by the
same three register writes. The correct pit pattern for Analog HI-Z is 110b. Use the following code to set port zero to
Analog HI-Z from Strong, by first going to Resistive Pull-down.