Cypress CY8C20xx7/S CapSense Series, Руководство по конструкции

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CapSense Technology
CY8C20xx7/S CapSense
®
Design Guide Doc. No. 001-78329 Rev. *E 16
Figure 2-8. CSDPLUS Block Diagram
Sigma Delta
Modulator
High Z
input
R
BUS
Modulation
I
DAC
Compensation
I
DAC
C
X
Precharge
clock
CY8C20xx7/S
V
REF
Switched-capacitor input
circuit converts
capacitance to current
External Connection
C
MOD
2.2 nF/X7R/5 V
Sigma delta converter converts current to digital counts
Analog Mux
Bus
Sw2
Sw1
2.2.2.1 Switched-Capacitor Input
The CSDPLUS method in CY8C20xx7/S devices incorporates C
X
into a switched-capacitor circuit, as Figure 2-9
shows.
Figure 2-9. Pin Configured as Switched-Capacitor Input
Analog Mux Bus
(AMUXBUS)
Discharge
Clock
Break-
Before-Make
Circuitry
Pin
C
X
Sw2
Sw1
Two non-overlapping, out-of-phase clocks of frequency F
SW
(see Figure 2-11 ) control switches Sw1 and Sw2. The
continuous switching of Sw1 and Sw2 forms an equivalent resistance R
S
, as Figure 2-10 shows. The value of the
equivalent resistance R
S
is:
R
S
=
1
C
X
F
SW
Equation 2-7
Where:
C
X
= Sensor capacitance
F
SW
= Frequency of the switching clock