CapSense Technology
CY8C20xx7/S CapSense
®
Design Guide
Doc. No. 001-78329 Rev. *E
13
Figure 2-3. CSD Block Diagram
Sigma Delta
Modulator
High Z
input
R
BUS
Modulation
I
DAC
C
X
Precharge
clock
CY8C20xx7/S
V
REF
Switched-capacitor input
circuit converts
capacitance to current
External Connection
C
MOD
2.2nF/X7R/5V
Sigma delta converter converts current to digital counts
Analog Mux
Bus
Sw2
Sw1
2.2.1.1 Switched-Capacitor Input
The CSD method in the CY8C20xx7/S device incorporates C
X
into a switched capacitor circuit, as
Figure 2-4. Pin Configured as Switched-Capacitor Input
Analog Mux Bus
(AMUXBUS)
Discharge
Clock
Break-
Before-Make
Circuitry
Pin
C
X
Sw2
Sw1
Two non-overlapping, out-of-phase clocks of frequency F
SW
) control the switches Sw1 and Sw2. The
continuous switching of Sw1 and Sw2 forms an equivalent resistance R
S
, as
equivalent resistance R
S
is:
R
S
=
1
C
X
F
SW
Equation 2-4
Where:
C
X
= Sensor capacitance
F
SW
= Frequency of the switching clock
