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Low-Power Design Considerations
CY8C20xx7/S CapSense
®
Design Guide
Doc. No. 001-78329 Rev. *E
67
PRT0DM0 = 0x00; // low bits
PRT0DM1 = 0xff; // med bits
PRT0DM2 = 0xff; //high bits
8.1.2 Putting it All Together
The following code is a sample of a typical sleep preparation sequence for a 28-pin part. In this sequence, interrupts
are disabled, the analog circuitry is turned off, all drive modes are set to Analog HI-Z, and interrupts are re-enabled.
void PSoC_Sleep(void)
{
M8C_DisableGInt;
PRT0DM0 = 0x00; // port 0 drives
PRT0DM1 = 0xff;
PRT0DM2 = 0xff;
PRT1DM0 = 0x00; // port 1 drives
PRT1DM1 = 0xff;
PRT1DM2 = 0xff;
PRT2DM0 = 0x00; // port 2 drives
PRT2DM1 = 0xff;
PRT2DM2 = 0xff;
M8C_EnableGInt;
M8C_Sleep;
}
8.1.3 Recommended I
2
C Slave Implementation in Sleep Mode
When I
2
C is used in sleep mode, certain implementation guidelines must be followed to keep the I
2
C bus from locking
or corrupted transactions from occurring.
8.1.3.1 Entry into I
2
C Sleep Mode
In general, the I
2
C slave must be put into a FORCE_NACK mode before entering the sleep mode. These steps need
to be followed to enter the sleep mode correctly:
Select the mode of operation (clock stretch or NACK during sleep to wakeup) through CLK_STRETCH_EN bit of
the I2C_BP_EZ_CFG register
Set the FORCE_NACK bit of the I2C_XCFG register
Poll status bit I2C_XSTAT.READY_TO_NACK for logic „1‟
Set the I2C_ON bit in the SLP_CFG2 register
Call the M8C_Sleep function (this sets the SLEEP bit (Bit 3) within the CPU_SCR0 register)
Note:
Data retention during sleep and deep sleep modes in the 32-byte I
2
C buffer is guaranteed only if power to the
I
2
C block is enabled by asserting I2C_ON bit in the SLP_CFG2 register.
8.1.4 Sleep Mode Complications
The CapSense controller can exit sleep either from a reset or through an interrupt. The CapSense controller has
three types of resets: External Reset, Watchdog Reset, and Power-On Reset. Any of these resets takes the
CapSense controller out of sleep mode. After the reset deasserts, the CapSense controller begins executing code
starting at
Boot.asm
. Available interrupts to wake the CapSense controller are: Sleep Timer, Low-Voltage Monitor,
GPIO, Analog Column, and Asynchronous. Sleep mode complications arise when using interrupts to wake the
CapSense controller or attempting digital communication while asleep. These considerations are discussed in detail
in the following sections.
8.1.5 Pending Interrupts
If an interrupt is pending, enabled, and scheduled to occur after a write to the SLEEP bit in the CPU_SCR0 register,
the system will not go to sleep. The instruction still executes, but the CapSense controller does not set the SLEEP bit.
Instead, the interrupt is serviced, which effectively causes the CapSense controller to ignore the sleep instruction. To
avoid this, interrupts should be globally disabled while sleep preparation occurs and then re-enabled just before
writing the SLEEP bit.