Cypress Semiconductor FLEx36 CY7C0850AV Скачать руководство пользователя

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FLEx36™ 3.3V 32K/64K/128K/256K x 36

Synchronous Dual-Port RAM

CY7C0850AV, CY7C0851AV

CY7C0852AV, CY7C0853AV

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Document #: 38-06070 Rev. *H

Revised July 29, 2008

Features

■

True dual-ported memory cells that allow simultaneous access

of the same memory location

■

Synchronous pipelined operation

■

Organization of 1-Mbit, 2-Mbit, 4-Mbit, and 9-Mbit devices

■

Pipelined output mode allows fast operation

■

0.18-micron CMOS for optimum speed and power

■

High-speed clock to data access

■

3.3V low power

❐

Active as low as 225 mA (typ)

❐

Standby as low as 55 mA (typ)

■

Mailbox function for message passing

■

Global master reset

■

Separate byte enables on both ports

■

Commercial and industrial temperature ranges

■

IEEE 1149.1-compatible JTAG boundary scan

■

172-Ball FBGA (1 mm pitch) (15 mm × 15 mm)

■

176-Pin TQFP (24 mm × 24 mm × 1.4 mm)

■

Counter wrap around control

❐

Internal mask register controls counter wrap-around

❐

Counter-interrupt flags to indicate wrap-around

❐

Memory block retransmit operation

■

Counter readback on address lines

■

Mask register readback on address lines

■

Dual Chip Enables on both ports for easy depth expansion

Functional Description

The FLEx36™ family includes 1M, 2M, 4M, and 9M pipelined,

synchronous, true dual-port static RAMs that are high-speed,

low-power 3.3V CMOS. Two ports are provided, permitting

independent, simultaneous access to any location in memory.

The result of writing to the same location by more than one port

at the same time is undefined. Registers on control, address, and

data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle

time. Each port contains a burst counter on the input address

address, the counter increments the address internally (more

details to follow). The internal Write pulse width is independent

of the duration of the R/W input signal. The internal Write pulse

is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down

the internal circuitry to reduce the static power consumption. One

cycle with chip enables asserted is required to reactivate the

outputs.
Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap-around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).
The CY7C0853AV device in this family has limited features.

Please see

See “Address Counter and Mask Register

Operations” on page 8.

for details.

Table 1. Product Selection Guide

Density

1-Mbit

(32K x 36)

2-Mbit

(64K x 36)

4-Mbit

(128K x 36)

9-Mbit

(256K x 36)

Part Number

CY7C0850AV

CY7C0851AV

CY7C0852AV

CY7C0853AV

Max. Speed (MHz)

167

133

Max. Access Time - Clock to Data (ns)

4.0

4.7

Typical operating current (mA)

225

270

Package

176TQFP

172FBGA

176TQFP

172FBGA

176TQFP

172FBGA

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Содержание FLEx36 CY7C0850AV

Страница 1: ... the same location by more than one port at the same time is undefined Registers on control address and data lines allow for minimal setup and hold time During a Read operation data is registered for decreased cycle time Each port contains a burst counter on the input address register After externally loading the counter with the initial address the counter increments the address internally more d...

Страница 2: ...MRST DQ9L DQ17L DQ0L DQ8L I O Control 9 9 9 9 DQ18L DQ26L DQ27L DQ35L CE0L CE1L R WL B0L B1L B2L B3L OEL A0R A17R CLKR ADS CNTEN CNTRSTR 18 Addr Read Back CNTINTR Mask Register Counter Address Register CNT MSKR Address Decode Interrupt Logic INTR DQ9R DQ17R DQ0R DQ8R I O Control 9 9 9 9 DQ18R DQ26R DQ27R DQ35R CE0R CE1R R WR B0R B1R B2R B3R OER Mirror Reg Mirror Reg Note 1 9M device has 18 address...

Страница 3: ...S VDD VDD B0R CE1R A5R A4R F VDD A6L A7L B1L VDD VSS B1R A7R A6R VDD G OEL B2L B3L CE0L CY7C0850AV CY7C0851AV CY7C0852AV CE0R B3R B2R OER H VSS R WL A8L CLKL CLKR A8R R WR VSS J A9L A10L VSS ADSL VSS VDD ADSR MRST A10R A9R K A11L A12L A15L 2 CNTRSTL VDD VDD VSS VDD CNTRSTR A15R 2 A12R A11R L CNT MSKL A13L CNTENL DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R CNTENR A13R CNT MSKR M A16L 2 A14L DQ22L D...

Страница 4: ...DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R E A4L A5L VDD B0L VDD VSS VDD VDD B0R VDD A5R A4R F VDD A6L A7L B1L VDD VSS B1R A7R A6R VDD G OEL B2L B3L VSS CY7C0853AV VSS B3R B2R OER H VSS R WL A8L CLKL CLKR A8R R WR VSS J A9L A10L VSS VSS VSS VDD VSS MRST A10R A9R K A11L A12L A15L VDD VDD VDD VSS VDD VDD A15R A12R A11R L VDD A13L VSS DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R VSS A13R VDD ...

Страница 5: ... 15L DQ 17L DQ 14L DQ 13L V SS V DD DQ 12L DQ 11L DQ 10L DQ 9L DQ 9R DQ 10R DQ 11R DQ 12R V DD V SS DQ 13R DQ 14R DQ 17R DQ 15R DQ 16R CNTINT R INT R DQ 27R DQ 29R DQ 28R DQ 30R V SS V DD DQ 31R DQ 32R DQ 33R DQ 26L DQ 23L DQ 22L V DD V SS DQ 21L DQ 25L DQ 19L DQ 18L TDI TDO DQ 8L DQ 7L DQ 6L DQ 5L DQ 4L V SS V DD DQ 3L DQ 2L DQ 1L DQ 0L DQ 0R DQ 1R DQ 2R DQ 3R V DD V SS DQ 4R DQ 5R DQ 6R DQ 7R DQ...

Страница 6: ...l must be asserted LOW to enable the DQ data pins during Read operations INTL INTR Mailbox Interrupt Flag Output The mailbox permits communications between ports The upper two memory locations can be used for message passing INTL is asserted LOW when the right port writes to the mailbox location of the left port and vice versa An interrupt to a port is deasserted HIGH when it reads the contents of...

Страница 7: ...etting the interrupt If an application does not require message passing INT pins should be left open Table 2 Interrupt Operation Example 1 4 5 6 7 Function Left Port Right Port R WL CEL A0L 17L INTL R WR CER A0R 17R INTR Set Right INTR Flag L L 3FFFF X X X X L Reset Right INTR Flag X X X X H L 3FFFF H Set Left INTL Flag X X X L L L 3FFFE X Reset Left INTL Flag H L 3FFFE H X X X X Table 3 Address C...

Страница 8: ...ST Counter Load Operation The address counter and mirror registers are both loaded with the address value presented at the address lines Counter Readback Operation The internal value of the counter register can be read out on the address lines Readback is pipelined the address is valid tCA2 after the next rising edge of the port s clock If address readback occurs while the port is enabled CE0 LOW ...

Страница 9: ...any external logic Mask Reset Operation The mask register is reset to all 1s which unmasks every bit of the counter Master reset MRST also resets the mask register to all 1s Mask Load Operation The mask register is loaded with the address value presented at the address lines Not all values permit correct increment opera tions Permitted values are of the form 2n 1 or 2n 2 From the most significant ...

Страница 10: ...ister Mirror Counter Address Decode RAM Array Wrap 1 0 Increment Logic 1 0 1 2 1 0 Wrap Detect From Mask From Counter To Counter Bit 0 Wrap 17 17 17 17 17 1 0 Load Increment CNT MSK CNTEN ADS CNTRST CLK Decode Logic Bidirectional Address Lines Mask Register Counter Address Register From Address Lines To Readback and Address Decode 17 17 MRST Feedback ...

Страница 11: ...16 215 26 21 25 22 24 23 20 216 215 26 21 25 22 24 23 20 216 215 26 21 25 22 24 23 20 H H L H 1 1 0s 1 0 1 0 1 0 1 0 0 Xs 1 X 0 X 0 X 0 1 1 Xs 1 X 1 X 1 X 1 0 0 Xs 1 X 0 X 0 X 0 Masked Address Unmasked Address Mask Register bit 0 Address Counter bit 0 CNTINT Example Load Counter Mask Register 3F Load Address Counter 8 Max Address Register Max 1 Address Register Feedback ...

Страница 12: ...ion Number 31 28 0h Reserved for version number Cypress Device ID 27 12 C001h Defines Cypress part number for the CY7C0851AV C002h Defines Cypress part number for the CY7C0852AV and CY7C0853AV C092h Defines Cypress part number for the CY7C0850AV Cypress JEDEC ID 11 1 034h Allows unique identification of the DP family device vendor ID Register Presence 0 1 Indicates the presence of an ID register T...

Страница 13: ... Leakage Current Except TDI TMS MRST 10 10 10 10 10 10 μA IIX2 Input Leakage Current TDI TMS MRST 0 1 1 0 0 1 1 0 0 1 1 0 mA ICC Operating Current for VDD Max IOUT 0 mA Outputs Disabled CY7C0850AV CY7C0851AV CY7C0852AV 225 300 225 300 mA CY7C0853AV 270 400 200 310 ISB1 18 Standby Current Both Ports TTL Level CEL and CER VIH f fMAX 90 115 90 115 90 115 mA ISB2 18 Standby Current One Port TTL Level ...

Страница 14: ...yte Select Setup Time 2 3 2 5 2 5 3 0 ns tHB Byte Select Hold Time 0 6 0 6 0 6 0 6 ns tSC Chip Enable Setup Time 2 3 2 5 NA NA ns tHC Chip Enable Hold Time 0 6 0 6 NA NA ns tSW R W Setup Time 2 3 2 5 2 5 3 0 ns tHW R W Hold Time 0 6 0 6 0 6 0 6 ns tSD Input Data Setup Time 2 3 2 5 2 5 3 0 ns tHD Input Data Hold Time 0 6 0 6 0 6 0 6 ns tSAD ADS Setup Time 2 3 2 5 NA NA ns tHAD ADS Hold Time 0 6 0 6...

Страница 15: ...7 0 5 7 5 0 5 7 5 0 5 10 ns tSCINT Clock to CNTINT Set Time 0 5 5 0 0 5 5 7 NA NA NA NA ns tRCINT Clock to CNTINT Reset time 0 5 5 0 0 5 5 7 NA NA NA NA ns Port to Port Delays tCCS Clock to Clock Skew 5 2 6 0 6 0 8 0 ns Master Reset Timing tRS Master Reset Pulse Width 7 0 7 5 7 5 10 0 ns tRSS Master Reset Setup Time 6 0 6 0 6 0 8 5 ns tRSR Master Reset Recovery Time 6 0 7 5 7 5 10 0 ns tRSF Master...

Страница 16: ... Time 40 ns tTL TCK Clock LOW Time 40 ns tTMSS TMS Setup to TCK Clock Rise 10 ns tTMSH TMS Hold After TCK Clock Rise 10 ns tTDIS TDI Setup to TCK Clock Rise 10 ns tTDIH TDI Hold After TCK Clock Rise 10 ns tTDOV TCK Clock LOW to TDO Valid 30 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns Figure 7 JTAG Switching Waveform Test Clock Test Mode Select TCK TMS Test Data In TDI Test Data Out TDO tTCYC tTMSH ...

Страница 17: ...2 An 3 tSC tHC tOHZ tOE tOLZ tDC tCD2 tCKLZ Qn Qn 1 Qn 2 1 Latency B0 B3 tSB tHB Notes 22 OE is asynchronously controlled all other inputs excluding MRST and JTAG are synchronous to the rising clock edge 23 ADS CNTEN LOW and MRST CNTRST CNT MSK HIGH 24 The output is disabled high impedance state by CE VIH following the next rising edge of the clock 25 Addresses do not have to be accessed sequentia...

Страница 18: ...4 Qn Qn 3 Qn 1 tCD2 tCD2 tCKLZ Notes 26 In this depth expansion example B1 represents Bank 1 and B2 is Bank 2 each bank consists of one Cypress CY7C0851AV CY7C0852AV device from this data sheet ADDRESS B1 ADDRESS B2 27 ADS CNTEN B0 B3 OE LOW MRST CNTRST CNT MSK HIGH 28 Output state HIGH LOW or high impedance is determined by the previous cycle control signals 29 During No Operation data in memory ...

Страница 19: ...rms continued tCYC2 tCL2 tCH2 tHC tSC tHW tSW tHA tSA An An 1 An 2 An 3 An 4 An 5 tHW tSW tSD tHD Dn 2 tCD2 tOHZ READ READ WRITE Dn 3 Qn CLK CE R W ADDRESS DATAIN DATAOUT OE Qn 4 tCD2 Qn 1 tCD2 tSA tHA tCH2 tCL2 tCYC2 CLK ADDRESS An COUNTER HOLD READ WITH COUNTER tSAD tHAD tSCN tHCN tSAD tHAD tSCN tHCN Qx 1 Qx Qn Qn 1 Qn 2 Qn 3 tDC tCD2 READ WITH COUNTER READ EXTERNAL ADDRESS ADS CNTEN DATAOUT Fee...

Страница 20: ... tCL2 tCYC2 An An 1 An 2 An 3 An 4 Dn 1 Dn 1 Dn 2 Dn 3 Dn 4 An Dn tSAD tHAD tSCN tHCN tSD tHD WRITE EXTERNAL WRITE WITH COUNTER ADDRESS WRITE WITH COUNTER WRITE COUNTER HOLD CLK ADDRESS INTERNAL DATAIN ADDRESS tSA tHA CNTEN ADS tCD2 CLK CE R W ADDRESS DATAOUT OE An An 1 An 2 An 3 An 4 Qn Qn 1 Qn 2 tCL2 tCH2 tCYC2 tSA tHA tSC tHC tHW tSW tHW tSW tSA tHA DISABLED READ WRITE READ READ READ DATAIN Dn ...

Страница 21: ... Switching Waveforms continued CLK CE R W ADDRESS OE DATAIN An An 1 An 2 An 3 An 4 tCL2 tCH2 tCYC2 tSC tHC tHW tSW tSA tHA tCD2 Dn Dn 2 DATAOUT Qn 1 tSD tHD Qn 3 DISABLED WRITE READ WRITE READ READ tOE CLK CE R W ADDRESS OE DATAIN An An 1 An 2 An 3 An 4 tCL2 tCH2 tCYC2 DATAOUT Dn 2 Qn tSC tHC tHW tSW tSA tHA tSD tHD tCD2 DISABLED WRITE READ READ READ DISABLED tOE tOHZ Qn 3 Feedback ...

Страница 22: ... Readback to Read to Read R W HIGH Switching Waveforms continued CLK ADS ADDRESS OE DATAOUT CNTEN COUNTER INTERNAL ADDRESS tCL2 tCH2 tCYC2 An 1 An 2 An 3 An 4 An An 1 Qn 1 Qn 2 Qn 3 tSAD tHAD tSCN tHCN tSA tHA READ NO OPERATION READ READ READ READBACK INCREMENT INCREMENT INCREMENT INCREMENT Feedback ...

Страница 23: ...n Q0 D0 tCH2 tCL2 tCYC2 tSA tHA tSW tHW tSRST tHRST tSD tHD tCD2 tCD2 tCKLZ 34 RESET ADDRESS 0 COUNTER WRITE READ ADDRESS 0 ADDRESS 1 READ READ ADDRESS An ADDRESS Am READ Notes 32 CE0 B0 B3 LOW CE1 MRST CNT MSK HIGH 33 No dead cycle exists during counter reset A Read or Write cycle may be coincidental with the counter reset 34 Retransmit happens if the counter remains in increment mode after it wr...

Страница 24: ...AL ADDRESS An 1 An 2 An tCKHZ DATAOUT An Qn 3 Qn 1 Qn 2 An 3 An 4 tCKLZ tCA2 or tCM2 READBACK INTERNAL COUNTER ADDRESS INCREMENT EXTERNAL A0 A16 Notes 35 CE0 OE B0 B3 LOW CE1 R W CNTRST MRST HIGH 36 Address in output mode Host must not be driving address bus after tCKLZ in next clock cycle 37 Address in input mode Host can drive address bus after tCKHZ 38 An is the internal value of the address co...

Страница 25: ...S R_PORT DATAOUT Notes 39 CE0 OE ADS CNTEN B0 B3 LOW CE1 CNTRST MRST CNT MSK HIGH 40 This timing is valid when one port is writing and other port is reading the same location at the same time If tCCS is violated indeterminate data is Read out 41 If tCCS minimum specified value then R_Port is Read the most recent data written by L_Port only 2 tCYC2 tCD2 after the rising edge of R_Port s clock If tC...

Страница 26: ...tCYC2 CLK 1FFFD 1FFFF INTERNAL ADDRESS Last_Loaded Last_Loaded 1 tHCM COUNTER 1FFFE CNTINT tSCINT tRCINT 1FFFC CNTEN ADS CNT MSK tSCM Notes 42 CE0 OE B0 B3 LOW CE1 R W CNTRST MRST HIGH 43 CNTINT is always driven 44 CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value 45 The mask register assumed to have the value of 1FFFFh Feedback ...

Страница 27: ...An An 1 An 2 L_PORT ADDRESS Am Am 4 Am 1 3FFFF Am 3 R_PORT ADDRESS INTR tSA tHA tSINT tRINT Notes 46 CE0 OE ADS CNTEN LOW CE1 CNTRST MRST CNT MSK HIGH 47 Address 3FFFF is the mailbox location for R_Port of a 9M device 48 L_Port is configured for Write operation and R_Port is configured for Read operation 49 At least one byte enable B0 B3 is required to be active during interrupt operations 50 Inte...

Страница 28: ... 24 x 24 x 1 4 mm CY7C0852AV 133AXI 176 Pin Thin Quad Flat Pack 24 x 24 x 1 4 mm Pb Free 64K 36 2M 3 3V Synchronous CY7C0851AV Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C0851AV 167BBC 51 85114 172 Ball Grid Array 15 x 15 x 1 25 mm with 1 mm pitch Commercial CY7C0851AV 167BBXC 172 Ball Grid Array 15 x 15 x 1 25 mm with 1 mm pitch Pb Free CY7C0851AV 1...

Страница 29: ...CY7C0850AV CY7C0851AV CY7C0852AV CY7C0853AV Document 38 06070 Rev H Page 29 of 32 Package Diagrams Figure 24 172 Ball FBGA 15 x 15 x 1 25 mm 51 85114 51 85114 B Feedback ...

Страница 30: ...CY7C0850AV CY7C0851AV CY7C0852AV CY7C0853AV Document 38 06070 Rev H Page 30 of 32 Figure 25 176 Pin Thin Quad Flat Pack 24 24 1 4 mm 51 85132 Package Diagrams 51 85132 Feedback ...

Страница 31: ...n write to a certain location while another port is reading that location from Functional Description D 238938 See ECN WWZ Merged 0853 9Mx36 with 0852 4Mx36 and 0851 2Mx36 add 0850 1M x36 to the data sheet Added product selection table Added JTAG ID code for 1M device Added note 14 Updated boundary scan section Updated function description for the merge and addition E 329122 See ECN SPN Updated Ma...

Страница 32: ...irmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH ...

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