Curtiss-Wright SCRAMNet+ SC150 VME6U, Справочник по аппаратуре

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OPERATION
Copyright 2007 5-14 VME6U HARDWARE REFERENCE
5.8.2 Network Error
The second interrupt condition is designed to intercept network errors. CSR1 contains the
following error conditions that may be masked by CSR9:
Table 5-4 Interrupt Error/Status Conditions
Bit Interrupt
0 Transmit FIFO Full
1 Transmit FIFO Not Empty
2
Transmit FIFO
⅞
Full
3 (Not masked for errors)
4 Interrupt FIFO Full
5 Protocol Violation
6 Carrier Detect Failure
7 Bad Message
8 Receiver Overflow
9 Transmit Retry
10 Transmit Retry Time-out
11 Redundant Rx/Tx Fault
12 General Purpose Counter/Timer
13 (Not masked for errors)
14 (Not masked for errors)
15 Fiber Optic Bypass Not Connected
Each of these conditions is identified by the corresponding bit being set (value 1) in
CSR1. If any of the preceding conditions are set and Interrupt On Memory Mask Match
Enable CSR0[5] is set, then an interrupt will be generated to the host computer.
Additional information about each error condition is contained in Appendix B, Table B-
2: CSR1.
If a Network Error is received (Figure 5-3), and if Interrupt on Error CSR0[7] and Host
Interrupt Enable CSR0[3] are set, and Interrupts are Enabled CSR1[14], then the message
generates an interrupt to the host. If additional network data interrupts occur before the
processor is able to service the interrupt, those shared-memory locations are updated and
the addresses are added to the Interrupt FIFO queue. However, no additional interrupt
signals are sent to the host until interrupts are armed by writing to CSR1.
There must also be an interrupt vector to the Interrupt Service Routine. The data vector is
stored in CSR6, and the error vector is in CSR7. CSR6 is associated with a memory
update and CSR7 is used to identify an error interrupt. Details are included in the
Programmer’s Reference Guide
for the host computer interface.