Curtiss-Wright SCRAMNet+ SC150 VME6U, Справочник по аппаратуре

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OPERATION
Copyright 2007 5-3 VME6U HARDWARE REFERENCE
5.2.2 Memory Considerations
When using SCRAMNet
+
shared-memory, consider the following:
PROGRAM AND DATA LIMITATIONS
Limitations on application program size and data variable size for a host computer system
also apply to applications that use SCRAMNet
+
memory because it becomes part of the
host system.
DATA CACHING
The ability for a computer to write a copy of data to a local fast memory for quicker
access later must be turned off during a SCRAMNet
+
memory read. Since other nodes
may be changing the data, it is critical that the processor read the data directly from
SCRAMNet
+
memory. This is processor dependent and does not always apply.
MEMORY MAPPING
SCRAMNet
+
memory is mapped by all operating systems in constant-length blocks
called memory pages.
NOTE
: To ensure that a compiler or operating system does not try to use unused
portions of SCRAMNet
+
memory to store other program segments, the SCRAMNet
+
memory common blocks should be declared to be sized to an integer multiple of the
processor memory page size. If this is not done, most compilers will try to optimize
memory usage by filling out the SCRAMNet
+
memory pages with other data. This can
cause random results when this local data is transmitted around the network.
5.2.3 Control/Status Registers
The SCRAMNet
+
boards are controlled through CSRs for node status, setting interrupt
vectors, setting interrupt locations, receiving interrupt addresses, mode control, and other
functions. These registers may be accessed by linking to the I/O page and reading from or
writing to the registers as if they were memory. The method used to access the registers
depends on the particular computer and operating system being used.
These registers are set only during the SCRAMNet
+
Network initialization. Once the
control portion of the CSR is set up for the desired mode operation, the node functions as
transparent shared memory, and, references to the CSRs are not required. However, the
status portions of the registers will need to be accessed for interrupt servicing and for
checking for error conditions. Appendix B, CSR DESCRIPTIONS, discusses the
definition and use of each bit in the CSRs. Appendix C contains a list of the CSRs and a
brief identification of each bit.
5.3 Initialization
The initialization of the SCRAMNet
+
node from a cold boot is determined by the settings
of the EEPROM (see Chapter 4, INSTALLATION).
No fiber-optic cable connections are required to READ and WRITE to the local host’s
SCRAMNet
+
memory. The control registers CSR0 and CSR2 should both be zero at this
point, and SCRAMNet
+
memory is available for access. The memory address will remain
at ‘0’ and be disabled until programmed with the EEPROM Initialization Program.