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REHOSTABLE CMC FPDP INTERFACE
Copyright 2012 11-5 FibreXtreme HW Reference for FPDP Cards
Table 11-3 Signal Descriptions for FPDP Configuration Interface (P3)
Signal Name Signal
Direction
Signal Description
AD[15:0] AD[15:8] are
input
AD[7:0] are
Bi-directional
Register Address/Data Bus . This bus contains the address
of the desired register and one byte of this register's data.
The bit definitions for reads/writes are:
AD[15:13] = don’t cares
AD[12:10] = register select
AD[9:8] = byte select
AD[7:0] = data
where
AD[12:10] CMC Register Accessed
000 0x00
001 0x04
010 0x08
011 0x0C
100 0x10
101 0x14
110 0x18
111 0x1C (not defined for SL100/SL240 CMC
register set)
AD[9:8] CMC Register Bits Accessed
00
7:0
01 15:8
10 23:16
11 31:24
When a register read is performed, AD[15:8] = "00000000"
is read back. For register reads/writes, the register bits are
shown in AD[7:0] in the following bit order: 31:24, 23:26,
15:8, 7:0. This does not mean the most significant byte must
be accessed first and the least significant byte must be
accessed last. The byte accessed is determined solely by
AD[9:8]. See section 11-9, microcontroller Interface, for
details.
/ADS Input Address Strobe . Set to ‘0’ to enable register access. Set to
‘1’ to disable register access. See section 11-9,
microcontroller Interface, for details.
CFG[1:0] Input Configuration Bus . These are the configuration signals for
the microcontroller interface. These are reserved for future
expansion, and should be driven as “00”.