CWdeb01 - BasicBoard
FPGA DEVELOPMENT AND EVALUATION BOARD
PRELIMINARY USER MANUAL, April 13, 2004
Copyright
2004, Coreworks, Lda
core
works, lda
http://www.coreworks.pt
1
BasicBoard
FPGA Development and Evaluation Board
User Manual
Страница 1: ...icBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004 Copyright 2004 Coreworks Lda coreworks lda http www coreworks pt 1 BasicBoard FPGA Development and Evaluation Board...
Страница 2: ...004 Coreworks Lda coreworks lda http www coreworks pt 2 TABLE OF CONTENTS FEATURES 3 DESCRIPTION 4 POWER SUPPLY 5 JUMPER SETTINGS 5 FPGA CONFIGURATION 5 BASICBOARD COMPONENTS 6 OSCILLATOR 6 LEDS 6 SEV...
Страница 3: ...th a capacity of 300 000 equivalent system gates Resources for basic lab work five pushbuttons eight LEDs four 7 segment displays and eight slide switches Includes a 55 MHz oscillator useful as a syst...
Страница 4: ...regulated For basic communication with a PC or other equipment the board includes an RS 232 port and a parallel port The parallel port is used to send the configuration file to the FPGA Alternatively...
Страница 5: ...ally the FPGA configuration is loaded from a PC In this situation the parallel port should be used The signals required by the JTAG programming mode pass throughout this port To support the JTAG mode...
Страница 6: ...ected to the FPGA GCK0 input pin 80 The oscillator module is assembled in an 8 pin socket labeled OSC When a different frequency is required this oscillator can be replaced by any compatible device LE...
Страница 7: ...B 193 C 192 D 191 E 189 F 188 G 187 Point 181 Table 3 FPGA pins for the segment drivers latches SLIDE SWITCHES The BasicBoard contains an array of eight slide switches When closed or ON each slide sw...
Страница 8: ...D 3 202 I Receive Data TXD 2 201 O Transmit Data DSR 6 200 O Data Set Ready RTS 7 198 I Request to Send CTS 8 199 O Clear to Send Table 6 FPGA pins for the RS 232 port 9 8 7 6 5 4 3 2 1 Figure 2 RS 23...
Страница 9: ...11 3 I Wait 12 not connected 13 not connected PDS 14 205 O Data Strobe 15 not connected PRS 16 203 O Reset PAS 17 204 O Address Strobe 18 25 Ground Table 8 FPGA pins for the parallel port EPP Mode 12...
Страница 10: ...Most of the pins available in the expansion connectors can be used as general purpose pins see Table 9 However some pins can be used to access specific resources in the FPGA Digital Looked Loops DLLs...
Страница 11: ...14 I O C13 166 I O D13 111 I O C14 165 I O D14 112 I O C15 164 I O D15 109 I O C16 163 I O D16 110 I O C17 162 I O D17 102 I O C18 20 I O D18 48 I O C19 GCK2 Input 182 I D19 100 I O C20 154 I O D20 10...
