Copyright
©
2016
congatec
AG
ICSLm13.indd
75/95
Feature
Options
Description
1-Core Ratio Limit Override
0
(more values)
This limit is for 1 cores active. ‘0’ sets the factory-configured value.
2-Core Ratio Limit Override
0
(more values)
This limit is for 2 cores active. ‘0’ sets the factory-configured value.
3-Core Ratio Limit Override
0
(more values)
This limit is for 3 cores active. ‘0’ sets the factory-configured value.
4-Core Ratio Limit Override
0
(more values)
This limit is for 4 cores active. ‘0’ sets the factory-configured value.
Configurable TDP Boot Mode
Nominal
Down
Up
Deactivate
The “Deactivate” option sets MSR to nominal and MMIO to zero.
Note:
Revision B.1 and older do not support TDP Up.
Configurable TDP Lock
Disabled
Enabled
Configurable TDP Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL.
Note:
When cTDP Lock is enabled, Custom ConfigTDP Count is forced to 1 and Custom ConfigTDP Boot Index is
forced to 0.
CTDP BIOS control
Disabled
Enabled
Enable or disable CTDP control via runtime ACPI BIOS methods.
Note:
This “BIOS only” feature does not require EC or driver support.
Platform PL1 Enable
Disabled
Enabled
Enable or disable the platform Power Limit 1 (PL1) programming.
If this option is enabled, the PL1 is used by the processor to limit the average power of a given time window.
Platform PL1 Power
0
(more values)
Platform Power Limit 1 Power in milliwatts and step size is 125mW. Any value can be programmed between
maximum and minimum power limits (specified by PACKAGE_POWER_SKU_MSR). This setting will act as the new
PL1 value for the Package RAPL algorithm.
Platform PL1 Time Window
0
(more values)
Platform Power Limit 1 Time Window value (in seconds). The value may vary from 0 to 128.
Platform PL2 Enable
Disabled
Enabled
Enable or disable the platform Power Limit 2 (PL2) programming.
If this option is disabled, the BIOS will program the default values for platform PL2.
Platform PL2 Power
0
(more values)
Platform Power Limit 2 Power in milliwatts and stepsize is 125mW. Any value can be programmed between
maximum and minimum power limits (specified by PACKAGE_POWER_SKU_MSR). This setting will act as the new
PL2 value for the Package RAPL algorithm.
CPU C States
Disabled
Enabled
Enable or disable CPU C states.
Enhanced C1 State
Disabled
Enabled
If this feature is enabled, the CPU will switch to minimum speed when all cores enter C-State.
C-State Auto Demotion
Disabled
C1
C3
C1 and C3
Configure C-State Auto Demotion.
C-State Un-demotion
Disabled
C1
C3
C1 and C3
Configure C-State Un-demotion.
Package C State Demotion
Disabled
Enabled
Configure C-State demotion.
