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Table 19 DisplayPort (DP) Signal Descriptions

Signal

Pin # Description

I/O

PU/PD

Comment

DP
DP1_LANE3-

D36
D37

Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI1_PAIR3-

O DP

DP
DP1_LANE2-

D32
D33

Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI1_PAIR2-

O DP

DP
DP1_LANE1-

D29
D30

Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI1_PAIR1-

O DP

DP
DP1_LANE0-

D26
D27

Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI1_PAIR0-

O DP

DP1_HPD

C24

Detection of Hot Plug / Unplug and notification of the link layer
Multiplexed with DDI1_HPD

I 3.3 V

PD 100 kΩ

D15

Half-duplex bi-directional AUX channel for services such as link configuration
or maintenance and EDID access

I/O DP

PD 100 kΩ

DP1_AUX-

D16

Half-duplex bi-directional AUX channel for services such as link configuration
or maintenance and EDID access

I/O DP

PU 100 kΩ
3.3 V

DP1_AUX- is a bootstrap signal (see note below).
DP enable strap is already populated

DP
DP2_LANE3-

D49
D50

Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI2_PAIR3-

O DP

DP
DP2_LANE2-

D46
D47

Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI2_PAIR2-

O DP

DP
DP2_LANE1-

D42
D43

Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI2_PAIR1-

O DP

DP
DP2_LANE0-

D39
D40

Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI1_PAIR0-

O DP

DP2_HPD

D44

Detection of Hot Plug / Unplug and notification of the link layer
Multiplexed with DDI2_HPD

I 3.3 V

PD 100 kΩ

C32

Half-duplex bi-directional AUX channel for services such as link configuration
or maintenance and EDID access

I/O DP

PD 100 kΩ

DP2_AUX-

C33

Half-duplex bi-directional AUX channel for services such as link configuration
or maintenance and EDID access

I/O DP

PU 100 kΩ
3.3 V

DP2_AUX- is a bootstrap signal (see note below).
DP enable strap already populated

DP
DP3_LANE3-

C49
C50

Uni-directional main link for the transport of isochronous streams and
secondary data
Multiplexed with DDI and DDI3_PAIR3-

O DP

Содержание 050700

Страница 1: ...COM Express conga TS570 11th Generation Intel Core i7 i5 i3 Celeron and Xeon processor with either QM580E HM570E or RM590E Chipset User s Guide Revision 0 1 Preliminary ...

Страница 3: ...congatec com en licenses Search for the revision of the BIOS UEFI or Board Controller Software as shown in the POST screen or BIOS setup to get the complete product related license information To the extent that any accompanying material such as instruction manuals handbooks etc contain copyright notices conditions of use or licensing requirements that contradict any applicable Open Source license...

Страница 4: ...arising out of or in connection with this user s guide or any other information contained herein or the use thereof Intended Audience This user s guide is intended for technically qualified personnel It is not intended for general audiences Lead Free Designs RoHS All congatec GmbH designs are created from lead free components and are completely RoHS compliant Electrostatic Sensitive Device All con...

Страница 5: ...tec GmbH All rights reserved All text pictures and graphics are protected by copyrights No copying is permitted without written permission from congatec GmbH congatec GmbH has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied as is Trademarks Product names logos brands and other trademarks featured or referred to within ...

Страница 6: ...he non conforming product freight prepaid congatec GmbH will pay for transporting the repaired or exchanged product to the customer Repaired replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired exchanged or replaced product is shipped by congatec or the remainder of the original warranty whichever is longer This Limited Warranty exten...

Страница 7: ...till require assistance after visiting our website then contact our technical support department by email at support congatec com Terminology Term Description DDI Digital Display Interface eDP Embedded DisplayPort EU Execution Units GB Gigabyte GHz Gigahertz HDA High Definition Audio kB Kilobyte kHz Kilohertz MB Megabyte Mbit Megabit MHz Megahertz N A Not available N C Not connected PCH Platform C...

Страница 8: ...30 5 1 6 USB 30 5 1 7 Gigabit Ethernet 31 5 1 8 High Definition Audio HDA 31 5 1 9 LPC Bus 31 5 1 10 I C Bus 32 5 1 11 GPIOs 32 5 1 12 General Purpose Serial Interface 32 5 1 13 Power Control 32 5 1 14 Power Management 35 6 Additional Features 36 6 1 congatec Board Controller cBC 36 6 1 1 Board Information 36 6 1 2 General Purpose Input Output 36 6 1 3 Watchdog 36 6 1 4 I2 C Bus 36 6 1 5 Power Los...

Страница 9: ...ns and Pinout Tables 46 8 1 Connector Signal Descriptions 47 8 2 Bootstrap Signals 69 9 System Resources 70 10 BIOS Setup Description 71 10 1 Navigating the BIOS Setup Menu 71 10 2 BIOS Versions 71 10 3 Updating the BIOS 72 10 3 1 Updating from External Flash 72 10 4 Supported Flash Devices 72 ...

Страница 10: ...t DP Signal Descriptions 57 Table 20 Embedded DisplayPort Signal Descriptions 58 Table 21 CRT Signal Descriptions 59 Table 22 LVDS Signal Descriptions 59 Table 23 Serial ATA Signal Descriptions 60 Table 24 USB 2 0 Signal Descriptions 60 Table 25 USB 3 0 Signal Descriptions 61 Table 26 Gigabit Ethernet Signal Descriptions 62 Table 27 High Definition Audio Link Signals Descriptions 63 Table 28 LPC S...

Страница 11: ...onents and is mounted onto an application specific carrier board COM modules are legacy free design no Super I O PS 2 keyboard and mouse and provide most of the functional requirements for any application These functions include but are not limited to a rich complement of contemporary high bandwidth serial interfaces such as PCI Express Serial ATA USB 2 0 and Gigabit Ethernet The Type 6 pinout pro...

Страница 12: ... 3200 MTps dual channel Non ECC Ethernet Controller Intel I225 LM Intel I225 LM Intel I225 V Intel I225 V Intel TSN TCC TSN TSN N A N A Processor TDP cTDP down 45 35 W 45 35 W 45 35 W 35 W Compatible Carrier Board conga TEVAL COMe 3 0 Evaluation Carrier Board for COM Express Type 6 modules Part No 050713 050714 050715 Processor Intel Xeon W 11865MLE 1 5 GHz 8 Core Intel Xeon W 11555MLE 1 9 GHz 6 C...

Страница 13: ... Intel UHD Graphics with 32 EU Intel UHD Graphics with 32 EU Intel UHD Graphics with 16 EU GFX Base Max Dynamic Freq 0 35 1 35 GHz 0 35 1 35 GHz 0 35 1 25 GHz DDR4 Memory ECC or non ECC 3200 MTps dual channel ECC or non ECC 3200 MTps dual channel ECC or non ECC 3200 MTps dual channel ECC or non ECC Ethernet Controller Intel I225 IT Intel I225 IT Intel I225 IT Intel TSN TCC TSN TCC TSN TCC TSN TCC ...

Страница 14: ...to four independent displays see table 10 Display Combination and Resolution 3x DP 1x LVDS eDP 4 1x VGA 5 1x PEG Gen 4 port x16 lanes Resolutions up to 4x4k 60 Hz NOTE The conga TS570 does not natively support TMDS For TMDS support a DP to TMDS converter e g PTN3360D needs to be implemented on the carrier board Peripheral Interfaces 8x USB 2 0 Up to 4x USB 3 2 Gen 2x1 4x SATA 6 Gbps with RAID 0 1 ...

Страница 15: ...the top upper slot is not populated in a dual memory configuration See section 7 5 SoDIMM Population Rules for more information 2 2 Supported Operating Systems The conga TS570 supports the following operating systems Microsoft Windows 10 64 bit Microsoft Windows 10 IoT Enterprise 64 bit Linux 64 bit Yocto Real Time Systems Hypervisor Note 1 The conga TS570 supports only native UEFI Operating Syste...

Страница 16: ...reader is shown below 2 4 Supply Voltage Standard Power 12V DC 5 The dynamic range shall not exceed the static range Heatspreader All dimensions in millimeter Module PCB Carrier Board PCB 13 00 5 00 or 8 00 4 00 5 00 4 50 2 00 10 7 00 Nominal Static Range Dynamic Range Absolute Minimum Absolute Maximum 12 60V 11 40V 12V 12 10V 11 90V ...

Страница 17: ...n Efficiency Max Load Power Watts VCC_12V 12 12 11 4 12 6 11 4 100 137 85 116 VCC_5V SBY 2 5 4 75 5 25 4 75 50 9 VCC_RTC 0 5 3 2 5 3 3 20 2 4 2 Rise Time The input voltages shall rise from 10 of nominal to 90 of nominal at a minimum slope of 250 V s The smooth turn on requires that during the 10 to 90 portion of the rise time the slope of the turn on waveform must be positive 2 5 Power Consumption...

Страница 18: ...umption The values were recorded at various operating mode Part No Memory Size H W Rev BIOS Rev OS 64 bit CPU Current Ampere Variant Cores Freq Turbo GHz S0 Min S0 Max S0 Peak S3 S5 S5e 050700 2 x 4 GB TBD TBD Windows 10 Intel Core i7 11850HE 8 2 6 4 7 TBD TBD TBD TBD TBD TBD 050701 2 x 4 GB TBD TBD Windows 10 Intel Core i5 11500HE 6 2 6 4 5 TBD TBD TBD TBD TBD TBD 050702 2 x 4 GB TBD TBD Windows ...

Страница 19: ...AN9_RTC_Battery_Lifetime pdf on congatec GmbH website at www congatec com support application notes 4 We recommend to always have a CMOS battery present when operating the conga TS570 2 7 Environmental Specifications Temperature commercial variants Operation 0 to 60 C Storage 20 to 80 C Temperature industrial variants Operation 40 to 85 C Storage 40 to 85 C up to 1 Gb Ethernet Temperature industri...

Страница 20: ...Ie Gen 3 eSPI SATA 6G PCIe USB 2 0 USB 3 1 HDA SPI0 MGMNT DMI Gen3 conga TS570 COM Express Rev 3 0 Basic Size Type 6 Pinout Dual Channel DDR4 SO DIMM ECC non ECC SPI Flash 0 TPM 2 0 Ethernet 10 100 1000 2500 Intel i225 LM V IT eDP to LVDS congatec Board Controller 5th Generation GPIOs eSPI SMB SMB UART I2C LID SLEEP FAN DP to VGA x4 NVMe SSD MUX MUX Ethernet SPI VGA LVDS eDP LPC SM Bus HDA I F I2C...

Страница 21: ...t can seep out over time depending on the environmental conditions it is subjected to For more information about this subject contact your local congatec sales representative and request the gap pad material manufacturer s specification Caution 1 The congatec heatspreaders cooling solutions are tested only within the commercial temperature range of 0 to 60 C If your application that features a con...

Страница 22: ...ec GmbH TSTLm01 22 72 4 1 CSA Dimensions 44 89 29 61 08 87 117 41 35 81 96 6 A A 2 1 2 7 TYP 1 2º TYP 125 15 TYP 20 TYP 2 x 0 6º M2 5 threaded standoff for threaded version or ø2 7 non threaded standoff for borehole version ...

Страница 23: ...c GmbH TSTLm01 23 72 4 2 CSP Dimensions 41 117 35 81 125 44 89 28 61 08 87 95 A 2 1 2 7 TYP A 1 2º TYP 125 15 TYP 20 TYP 2 x 0 6º M2 5 threaded standoff for threaded version or ø2 7 non threaded standoff for borehole version ...

Страница 24: ...opyright 2022 congatec GmbH TSTLm01 24 72 4 3 HSP Dimensions 41 117 35 81 125 44 89 11 61 08 87 95 M2 5 x 11 threaded standoff for threaded version or ø2 7 x 11 non threaded standoff for borehole version ...

Страница 26: ...he A B connector and two PCIe lanes on the C D connector The lanes support up to 8 GTps Gen 3 speed an 8 x1 link configuration a 2 x4 link a 4 x2 link 1 x4 2 x2 link or a 4 x1 1 x4 or 2 x2 link via a special customized BIOS firmware lane polarity inversion 5 1 2 PCI Express Graphics PEG The conga TS570 supports PEG x16 interface PCIe Gen 4 on the C D connector The interface supports PCI Express Sp...

Страница 27: ...wn in the diagram below PEG LANE 0 Single Link 1x16 Link Link 1 Link 1 Link 1 Link 2 Link 3 Link 2 Double Links 2x8 Links Triple Links 1x8 2x4 Links PEG LANE 1 PEG LANE 2 PEG LANE 3 PEG LANE 4 PEG LANE 5 PEG LANE 6 PEG LANE 7 PEG LANE 8 PEG LANE 9 PEG LANE 10 PEG LANE 11 PEG LANE 12 PEG LANE 13 PEG LANE 14 PEG LANE 15 ...

Страница 28: ...6 bpp LVDS or eDP 1920x1200 60 Hz dual LVDS mode 4096x2304 60 Hz 24 bpp Option 2 DP 4096x2304 60 Hz 36 bpp DP 4096x2304 60 Hz 36 bpp DP 4096x2304 60 Hz 36 bpp VGA 1920x1200 60 Hz Option 3 DP 4096x2304 60 Hz 36 bpp DP 4096x2304 60 Hz 36 bpp VGA 1920x1200 60 Hz LVDS or eDP 1920x1200 60 Hz dual LVDS mode 4096x2304 60 Hz 24 bpp Note A single DP eDP display supports maximum resolution of 5120x3200 60 H...

Страница 29: ...or mappings automatic panel detection via Embedded Panel Interface based on VESA EDIDTM 1 3 resolution up to 1920x1200 in dual LVDS channel mode The eDP 1 2 interface supports eDP 1 4 specification Spread Spectrum Clocking eDP display authentication Note 1 The LVDS eDP interface does not support LVDS and eDP signals at the same time 2 The eDP interface does not support HDCP 5 1 3 3 VGA The Intel T...

Страница 30: ...does not support hotplug 5 1 6 USB The conga TS570 offers eight USB 2 0 interfaces on the A B connector and up to four SuperSpeed signals on the C D connector The xHCI host controller supports USB 3 2 specification SuperSpeedPlus SuperSpeed High Speed Full Speed and Low Speed USB signaling data transfers of up to 10 Gbps for USB 3 2 Gen 2x1 port data transfers of up to 5 Gbps for USB 3 2 Gen 1x1 p...

Страница 31: ... a limitation of Ethernet Phy since it has only three LED outputs ACT LINK100 and LINK1000 2 The GBE0_LINK signal is a logic AND of the GBE0_LINK100 and GBE0_LINK1000 signals on the conga TS570 module 3 The Intel i225 IT Ethernet controller supports 2 5 Gb mode at temperature range of 40 C to 70 C and 1 Gb mode at temperature range of 40 C to 85 C 4 Not supported in Windows Operating Systems 5 1 8...

Страница 32: ...tor via the congatec Board Controller The interfaces support up to 115200 baud rate Note The UART interfaces do not support hardware handshake and flow control 5 1 13 Power Control PWR_OK Power OK from main power supply or carrier board voltage regulator circuitry A high value indicates that the power is good and the module can start its onboard power sequencing Carrier board hardware must drive t...

Страница 33: ...he module is kept in reset as long as the PWR_OK is driven by carrier board hardware The conga TS570 PWR_OK input circuitry is implemented as shown below To Module Power Logic PWR_OK R1 4k75S02 TBC847 R1 10kS02 V12 0_S0 R1 1k00S02 R1 47kS02 R1 20k0S02 ...

Страница 34: ... regulator in the chain on the carrier board Simply pull PWR_OK with a 1k resistor to the carrier board 3 3V power rail With this solution you must ensure that by the time the 3 3V is up all carrier board hardware is fully powered and all clocks are stable The conga TS570 supports the controlling of ATX style power supplies If you do not use an ATX power supply do not connect the conga TS570 pins ...

Страница 35: ...ough an oscilloscope during the power supply qualication phase This will help to determine if the rise is indeed monotonic and does not have any dips For more information see the Power Supply Design Guide for Desktop Platform Form Factors document at www intel com 5 1 14 Power Management ACPI The conga TS570 supports Advanced Configuration and Power Interface ACPI specification revision 4 0a It al...

Страница 36: ...the following features 6 1 1 Board Information The cBC provides a rich data set of manufacturing and board information such as serial number EAN number hardware and firmware revisions and so on It also keeps track of dynamically changing data like runtime meter and boot counter 6 1 2 General Purpose Input Output The conga TS570 offers general purpose inputs and outputs for custom system design The...

Страница 37: ...e the correct speed readout 2 For the correct fan control FAN_PWMOUT FAN_TACHIN implementation see the COM Express Design Guide 6 1 7 Enhanced Soft Off State The conga TS570 supports an enhanced Soft Off state S5e a congatec proprietary low power Soft Off state In this state the CPU module switches off almost all the onboard logic in order to reduce the power consumption to absolute minimum usuall...

Страница 38: ...em utility CGUTIL 1 5 4 or later to replace add the OEM POST logo 6 2 4 OEM DXE Driver This feature allows designers to add their own UEFI DXE driver to the congatec embedded BIOS Contact congatec technical support for more information on how to add an OEM DXE driver 6 3 congatec Battery Management Interface To facilitate the development of battery powered mobile systems based on embedded modules ...

Страница 39: ...vailable for all commonly used Operating Systems such as Win32 Win64 Win CE Linux The architecture of the CGOS API driver provides the ability to write application software that runs unmodified on all congatec CPU modules All the hardware related code is contained within the congatec embedded BIOS on the module See section 1 1 of the CGOS API software developers guide available on the congatec web...

Страница 40: ... core to reduce frequency and voltage adaptively The Adaptive Thermal Monitor will remain active as long as the package temperature remains at its specified limit Therefore the Adaptive Thermal Monitor will continue to reduce the package frequency and voltage until the TCC is de activated Clock modulation is activated if frequency and voltage adjustments are insufficient Additional hardware softwa...

Страница 41: ...cy control This feature is also referred to as Hardware controlled Performance States HWP It is a hardware implementation of the ACPI defined Collaborative Processor Performance Control CPPC2 and is supported by newer operating systems Win 8 1 or newer With this feature enabled the processor autonomously selects performance states based on workload demand and thermal limits while also considering ...

Страница 42: ...0 2 For real time sensitive applications disable EIST and Turbo Mode in the BIOS setup to ensure a more deterministic performance 3 Disable Turbo mode for industrial use condition applications 7 3 Intel Virtualization Technology Intel Virtualization Technology Intel VT makes a single system appear as multiple independent systems to software With this technology multiple independent operating syste...

Страница 43: ... thermal trip point on conga TS570 is the Critical Trip Point The active or passive cooling policy should ensure that the CPU temperature does not reach this trip point However if the critical trip point is reached the OS will shut down properly in order to prevent damage to the system Note Use the critical trip point setup node in the BIOS setup menu to determine the temperature threshold at whic...

Страница 44: ...2 V With this low voltage system memory interface the conga TS570 offers a system optimized for lowest possible power consumption The reduction in power consumption due to lower voltage subsequently reduces the heat generated The diagram below shows the location of the memory slots on the conga TS570 The following population rules must be observed For single memory module either of the top slots c...

Страница 45: ...el ECC with non interleave is not supported Table 11 Memory Population Compatibility The table below shows the possible memory combinations and their corresponding results Top Upper Slot Channel 0 DIMM 0 Top Lower Slot Channel 1 DIMM 0 Bottom Slot Channel 0 DIMM 1 Result x x x OK x x OK x x OK x OK x OK x Boot error POST Code 53 x x Boot error POST Code 53 ...

Страница 46: ...gnal Tables Terminology Descriptions Term Description PU Implemented pull up resistor PD Implemented pull down resistor I O 3 3V Bi directional signal 3 3 V tolerant I O 5V Bi directional signal 5 V tolerant I 3 3V Input 3 3 V tolerant I 5V Input 5 V tolerant I O 3 3VSB Input or output 3 3 V tolerant active in standby state O 3 3V Output 3 3 V signal level O 5V Output 5 V signal level OD Open drai...

Страница 47: ..._CK A68 PCIE_TX0 B68 PCIE_RX0 A14 GBE0_CTREF 1 B14 SMB_DAT A69 PCIE_TX0 B69 PCIE_RX0 A15 SUS_S3 B15 SMB_ALERT 3 A70 GND FIXED B70 GND FIXED A16 SATA0_TX B16 SATA1_TX A71 eDP_TX2 LVDS_A0 B71 LVDS_B0 A17 SATA0_TX B17 SATA1_TX A72 eDP_TX2 LVDS_A0 B72 LVDS_B0 A18 SUS_S4 B18 SUS_STAT ESPI_RESET A73 eDP_TX1 LVDS_A1 B73 LVDS_B1 A19 SATA0_RX B19 SATA1_RX A74 eDP_TX1 LVDS_A1 B74 LVDS_B1 A20 SATA0_RX B20 SA...

Страница 48: ...D B41 GND FIXED A96 TPM_PP B96 VGA_I2C_DAT A42 USB2 B42 USB3 A97 TYPE10 1 B97 SPI_CS A43 USB2 B43 USB3 A98 SER0_TX B98 RSVD 1 A44 USB_2_3_OC B44 USB_0_1_OC A99 SER0_RX B99 RSVD 1 A45 USB0 B45 USB1 A100 GND FIXED B100 GND FIXED A46 USB0 B46 USB1 A101 SER1_TX B101 FAN_PWMOUT A47 VCC_RTC B47 ESPI_EN 1 A102 SER1_RX B102 FAN_TACHIN A48 RSVD 1 B48 USB0_HOST_PRSNT 2 A103 LID B103 SLEEP A49 GBE0_SDP B49 S...

Страница 49: ...ND C69 PEG_RX5 D69 PEG_TX5 C15 DDI1_PAIR6 1 D15 DDI1_CTRLCLK_AUX C70 GND FIXED D70 GND FIXED C16 DDI1_PAIR6 1 D16 DDI1_CTRLDATA_AUX 3 C71 PEG_RX6 D71 PEG_TX6 C17 RSVD 1 D17 RSVD 1 C72 PEG_RX6 D72 PEG_TX6 C18 RSVD 1 D18 RSVD 1 C73 GND D73 GND C19 PCIE_RX6 D19 PCIE_TX6 C74 PEG_RX7 D74 PEG_TX7 C20 PCIE_RX6 D20 PCIE_TX6 C75 PEG_RX7 D75 PEG_TX7 C21 GND FIXED D21 GND FIXED C76 GND D76 GND C22 PCIE_RX7 D...

Страница 50: ...42 DDI3_PAIR1 D42 DDI2_PAIR1 C97 RVSD 1 D97 RSVD 1 C43 DDI3_PAIR1 D43 DDI2_PAIR1 C98 PEG_RX14 D98 PEG_TX14 C44 DDI3_HPD D44 DDI2_HPD C99 PEG_RX14 D99 PEG_TX14 C45 RSVD 1 D45 RSVD 1 C100 GND FIXED D100 GND FIXED C46 DDI3_PAIR2 D46 DDI2_PAIR2 C101 PEG_RX15 D101 PEG_TX15 C47 DDI3_PAIR2 D47 DDI2_PAIR2 C102 PEG_RX15 D102 PEG_TX15 C48 RSVD 1 D48 RSVD 1 C103 GND D103 GND C49 DDI3_PAIR3 D49 DDI2_PAIR3 C10...

Страница 51: ...press Base Specification Revision 3 0 PCIE_RX4 PCIE_RX4 B55 B56 PCI Express channel 4 Receive Input differential pair I PCIE Supports PCI Express Base Specification Revision 3 0 PCIE_TX4 PCIE_TX4 A55 A56 PCI Express channel 4 Transmit Output differential pair O PCIE Supports PCI Express Base Specification Revision 3 0 PCIE_RX5 PCIE_RX5 B52 B53 PCI Express channel 5 Receive Input differential pair ...

Страница 52: ...X8 PEG_RX9 PEG_RX9 PEG_RX10 PEG_RX10 PEG_RX11 PEG_RX11 PEG_RX12 PEG_RX12 PEG_RX13 PEG_RX13 PEG_RX14 PEG_RX14 PEG_RX15 PEG_RX15 C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C69 C71 C72 C74 C75 C78 C79 C81 C82 C85 C86 C88 C89 C91 C92 C94 C95 C98 C99 C101 C102 PCI Express Graphics Receive Input differential pairs Note Can also be used as PCI Express Receive Input differential pairs 16 through 31 known...

Страница 53: ...88 D89 D91 D92 D94 D95 D98 D99 D101 D102 PCI Express Graphics Transmit Output differential pairs Note Can also be used as PCI Express Transmit Output differential pairs 16 through 31 known as PCIE_TX 16 31 and O PCIE Supports PCI Express Base Specification Revision 4 0 PEG_LANE_RV 1 D54 PCI Express Graphics lane reversal input strap Pull low on the carrier board to reverse lane order I PU 10 kΩ 3 ...

Страница 54: ...RLDATA if DDI1_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3 V PU 100 kΩ 3 3V Bootstrap signal see note below Enable strap is already populated DDI1_DDC_AUX_SEL D34 Selects the function of DDI1_CTRLCLK_AUX and DDI1_CTRLDATA_AUX This pin shall have a IM pull down to logic ground on the module If this input is floating the AUX pair is used for the DP AUX signals If pulled high the AUX pair contains...

Страница 55: ...gh I ODP I O OD 3 3 V PD 100 kΩ DDI3_CTRLDATA_AUX 1 C37 Multiplexed with DP3_AUX and HDMI3_CTRLDATA DP AUX function if DDI3_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high I O DP I O OD 3 3 V PU 100 kΩ 3 3 V Bootstrap signal see note below Enable strap is already populated DDI3_DDC_AUX_SEL C38 Selects the function of DDI3_CTRLCLK_AUX and DDI3_CTRLDATA_AUX This pi...

Страница 56: ... C Control Data Multiplexed with DDI2_CTRLDATA_AUX I O OD 3 3 V PU 2k2 3 3 V Bootstrap signal see note below Enable strap is already populated TMDS3_CLK TMDS3_CLK C49 C50 TMDS Clock output differential pair Multiplexed with DDI3_PAIR3 and DDI3_PAIR3 O DP TMDS3_DATA0 TMDS3_DATA0 C46 C47 TMDS differential pair Multiplexed with DDI3_PAIR2 and DDI3_PAIR2 O DP TMDS3_DATA1 TMDS3_DATA1 C42 C43 TMDS diffe...

Страница 57: ...3 V DP1_AUX is a bootstrap signal see note below DP enable strap is already populated DP2_LANE3 DP2_LANE3 D49 D50 Uni directional main link for the transport of isochronous streams and secondary data Multiplexed with DDI2_PAIR3 and DDI2_PAIR3 O DP DP2_LANE2 DP2_LANE2 D46 D47 Uni directional main link for the transport of isochronous streams and secondary data Multiplexed with DDI2_PAIR2 and DDI2_P...

Страница 58: ...ID access I O DP PD 100 kΩ DP3_AUX 1 C37 Half duplex bi directional AUX channel for services such as link configuration or maintenance and EDID access I O DP PU 100 kΩ 3 3 V DP3_AUX is a bootstrap signal see note below DP enable strap already populated Note 1 These signals have special functionality during the reset process They may bootstrap some basic important functions of the module For more i...

Страница 59: ...e on industrial variants you need a customized conga TS570 variant assembly option Table 22 LVDS Signal Descriptions Signal Pin Description I O PU PD Comment LVDS_A0 LVDS_A0 LVDS_A1 LVDS_A1 LVDS_A2 LVDS_A2 LVDS_A3 LVDS_A3 A71 A72 A73 A74 A75 A76 A78 A79 LVDS Channel A differential pairs O LVDS LVDS_A_CK LVDS_A_CK A81 A82 LVDS Channel A differential clock O LVDS LVDS_B0 LVDS_B0 LVDS_B1 LVDS_B1 LVDS...

Страница 60: ...ctive low I O 3 3 V Table 24 USB 2 0 Signal Descriptions Signal Pin Description I O PU PD Comment USB0 B46 USB Port 0 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB0 B45 USB Port 0 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB1 A46 USB Port 1 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB1 A45 USB Port 1 data or D I O USB 2 0 complian...

Страница 61: ...An open drain driver from a USB current monitor on the carrier board may drive this line low I 3 3 VSB PU 10 kΩ 3 3 VSB USB0_HOST_ PRSNT B48 Module USB client may detect the presence of a USB host on USB0 A high value indicates that a host is present I 3 3 VSB PD 1 MΩ Not supported Table 25 USB 3 0 Signal Descriptions Signal Pin Description I O PU PD Comment USB_SSRX0 C4 Additional receive signal ...

Страница 62: ...F A14 Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap The reference voltage is determined by the requirements of the module PHY and may be as low as 0 V and as high as 3 3 V The reference voltage output shall be current limited on the module In the case in which the reference is shorted to ground the current shall be limited to 250 mA or less REF Not connected GBE0_SDP ...

Страница 63: ...tion I O PU PD Comment LPC_AD 0 3 B4 B7 LPC Mode LPC multiplexed address command and data bus I O 3 3 V PU 20 KΩ 3 3 V LPC_FRAME B3 LPC Mode LPC Frame indicates the start of a LPC cycle O 3 3 V LPC_CLK B10 LPC Mode LPC clock output 33MHz O 3 3 V LPC_DRQ 0 1 B8 B9 LPC Mode LPC serial DMA request I 3 3 V PU 100 KΩ 3 3 V LPC_SERIRQ A50 LPC Mode LPC serial interrupt I O 3 3 V PU 10 KΩ 3 3 V SUS_STAT B...

Страница 64: ...s have special functionality during the reset process They may bootstrap some basic important functions of the module For more information refer to section 8 2 Bootstrap Signals Table 30 Miscellaneous Signal Descriptions Signal Pin Description I O PU PD Comment I2C_CK B33 General purpose I C port clock output input I O 3 3 V PU 2K2 3 3 VSB I2C_DAT B34 General purpose I C port data I O line I O 3 3...

Страница 65: ...n hardware reset while this input is kept low Note For proper detection assert a pulse width of at least 16 ms I 3 3 VSB PU 10 kΩ 3 3 VSB CB_RESET B50 Active low reset output from module to Carrier Board Issued by module chipset and may occur from a low SYS_RESET input a low PWR_OK input a VCC_12V power input that falls below the minimum specification a watchdog timeout or may be initiated by the ...

Страница 66: ...nt RAPID_SHUTDOWN C67 Trigger for Rapid Shutdown Must be driven to 5V though a 50 ohm source impedance for 20 μs I 3 3 V Not connected Note The conga TS570 does not support Rapid Shutdown Table 34 Thermal Protection Signal Descriptions Signal Pin Description I O PU PD Comment THRM B35 Input from off module temp sensor indicating an over temp situation I 3 3 V PU 10 kΩ 3 3 V THRMTRIP A35 Active low...

Страница 67: ...xpress Type 6 pinout therefore the pins 0 and 1 are not connected and pin 2 is connected to GND TYPE2 TYPE1 TYPE0 X NC NC NC NC GND X NC NC GND GND NC X NC GND NC GND NC Pinout Type 1 Pinout Type 2 Pinout Type 3 no IDE Pinout Type 4 no PCI Pinout Type 5 no IDE no PCI Pinout Type 6 no IDE no PCI The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps powe...

Страница 68: ...d for standby and suspend functions May be left unconnected if these functions are not used in the system design P VCC_RTC A47 Real time clock circuit power input Nominally 3 0V P GND A1 A11 A21 A31 A41 A51 A57 A60 A66 A70 A80 A90 A100 A110 B1 B11 B21 B31 B41 B51 B60 B70 B80 B90 B100 B110 C1 C2 C5 C8 C11 C14 C21 C31 C41 C51 C60 C70 C73 C76 C80 C84 C87 C90 C93 C96 C100 C103 C110 D1 D2 D5 D8 D11 D14...

Страница 69: ...f DDI1_DDC_AUX_SEL is no connect I O PCIE HDMI1_CTRLDATA HDMI DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high I O OD 3 3 V DDI2_CTRLDATA_AUX C33 Multiplexed with DP2_AUX and HDMI2_CTRLDATA PU 2k2 3 3 V DP2_AUX DP AUX function if DDI2_DDC_AUX_SEL is no connect I O PCIE HDMI2_CTRLDATA HDMI DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high I O OD 3 3 V DDI3_CTRLDATA_AUX C37 Multiplexed with DP3...

Страница 71: ...m Note If you do not have access to the restricted area of the congatec website contact your local congatec sales representative 10 1 Navigating the BIOS Setup Menu The BIOS setup menu shows the features and options supported in the congatec BIOS To access and navigate the BIOS setup menu press the DEL or F2 key during POST The right frame displays the key legend Above the key legend is an area re...

Страница 72: ...t www congatec com Note 1 Deprecated Caution The DOS command line tool is not officially supported by congatec and therefore not recommended for critical tasks such as firmware updates We recommend to use only the UEFI shell for critical updates 10 3 1 Updating from External Flash For instructions on how to update the BIOS from external flash refer to the AN7_External_BIOS_Update pdf application n...

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