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Copyright © 2021 congatec GmbH
SA70m01
57/65
PCIE_
PCIE_B_REFCK-
S84
S85
Differential PCIe Link reference clock output DC coupled
O LVDS PCIe
PCIE_
PCIE_C_REFCK-
P80
P81
Differential PCIe Link reference clock output DC coupled
O LVDS PCIe
PCIE_A_RST#
P75
PCIe port reset output
O 3.3V
PCIE_B_RST#
S76
PCIe port reset output
O 3.3V
PCIE_C_RST#
S77
PCIe port reset output
O 3.3V
PCIE_WAKE#
S146
PCIe wake up interrupt to host common to PCIe links A, B, C, D
I OD 3.3V
PU 10k
Table 27 SERDES Signal Description
Signal Name
Pin
Description
I/O
PU/PD Comment
SERD
SERDES_1_TX-
S81
S82
Differential SERDES 1 Transmit Data Pair
O PCIE
Not supported
SERD
SERDES_1_RX-
S78
S79
Differential SERDES 1 Receive Data Pair
I PCIE
SERD
SERDES_0_TX-
S29
S30
Differential SERDES 0 Transmit Data Pair
O PCIE
SERD
SERDES_0_RX-
S32
S33
Differential SERDES 0 Receive Data Pair
I PCIE
MDIO_CLK
S45
MDIO Signals to Configure Possible PHYs
O 1.8V
MDIO_DAT
S46
MDIO Signals to Configure Possible PHYs
I/O OD 1.8V
Note
The conga-SA7 does not support SERDES.
Table 28 SATA Signal Description
Signal Name
Pin
Description
I/O
PU/PD Comment
SATA_TX-
P48
P49
SATA 0 transmit differential data pair
O SATA
Supports SATA specification, Revision 3.0
SATA_RX-
P51
P52
SATA 0 receive differential data pair
I SATA
Supports SATA specification, Revision 3.0
SATA_ACT#
S54
Active low SATA activity indicator
O OD 3.3V
Up to 24 mA LED current