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Copyright © 2021 congatec GmbH
SA70m01
56/65
USB0_VBUS_DET P63
USB host power detection when this port is used as a device
I USB VBUS 5V
PD 100k
Not supported
USB3_VBUS_DET S37
USB host power detection when this port is used as a device
I USB VBUS 5V
PD 100k
USB0_OTG_ID
USB3_OTG_ID
P64
S104
USB OTG ID input, active high
I 3.3V
PU 100k
U
USB2SSRX-
S74
S75
Receive signal differential pairs for SuperSpeed USB data
coupling caps for RX pairs are
off
-module
I USB SS
U
USB2SSTX-
S71
S72
Transmit signal differential pairs for SuperSpeed USB data
coupling caps for TX pairs are
on
-module
O USB SS
U
USB3SSRX-
S65
S66
Receive signal differential pairs for SuperSpeed USB data
coupling caps for RX pairs are
off
-module
I USB SS
U
USB3SSTX-
S62
S63
Transmit signal differential pairs for SuperSpeed USB data
coupling caps for TX pairs are
on
-module
O USB SS
Note
The conga-SA7 does not support USB OTG.
Table 26 PCIe Signal Description
Signal Name
Pin
Description
I/O
PU/PD
Comment
PC
PCIE_A_TX-
P89
P90
Differential PCIe link A transmit data pair
O LVDS PCIe
AC coupled with 220nF on module
PC
PCIE_B_TX-
S90
S91
Differential PCIe link B transmit data pair
O LVDS PCIe
AC coupled with 220nF on module
PC
PCIE_C_TX-
S81
S82
Differential PCIe link C transmit data pair
O LVDS PCIe
AC coupled with 220nF on module
PC
PCIE_D_TX-
S29
S30
Differential PCIe link D transmit data pair
O LVDS PCIe
AC coupled with 220nF on module
PC
PCIE_A_RX-
P86
P87
Differential PCIe link A receive data pair
I LVDS PCIe
PC
PCIE_B_RX-
S87
S88
Differential PCIe link B receive data pair
I LVDS PCIe
PC
PCIE_C_RX-
S78
S79
Differential PCIe link C receive data pair
I LVDS PCIe
PC
PCIE_D_RX-
S32
S33
Differential PCIe link D receive data pair
I LVDS PCIe
PCIE_
PCIE_A_REFCK-
P83
P84
Differential PCIe Link reference clock output DC coupled
O LVDS PCIe