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2017
congatec
AG
MA50m17
56/60
00h
016h
01h
0x5AAE
I2C 1
*2
00h
016h
02h
0x5AB0
I2C 2
*2
00h
016h
03h
0x5AB2
I2C 3
*2
00h
017h
00h
0x5AB4
I2C 4
*2
00h
017h
00h
0x5AB6
I2C 5
*2
00h
017h
00h
0x5AB8
I2C 6
*2
00h
017h
00h
0x5ABA
I2C 7
*2
00h
018h
00h
0x5ABC
SoC UART 0
*2
00h
018h
01h
0x5ABE
SoC UART 1
*2
00h
018h
02h
0x5AC0
SoC UART 2
*2
00h
018h
03h
0x5AEE
SoC UART 3
*2
00h
019h
00h
0x5AC2
SPI 0
*2
00h
019h
01h
0x5AC4
SPI 1
*2
00h
019h
02h
0x5AC6
SPI 2
*2
00h
01Bh
00h
0x5ACA
SD Card
00h
01Ch
01h
0x5ACC
eMMC
00h
01Fh
00h
0x5AE8
LPC Bus
00h
01Fh
01h
0x5AD4
SM Bus
02h
00h
00h
0x1539
Intel PCIe Ethernet Network on Module
Note
The above table represents a case when a single function PCI Express device is connected to all possible slots on the carrier board. The given
bus numbers will change based on actual hardware configuration.
*1
The PCI Express Ports may only be visible if the PCI Express Port is set to “Enabled” in the BIOS setup program and a device is attached
to the corresponding PCI Express port on the carrier board.
*2
This device is disabled as default in BIOS Setup.
9.3
I²C Bus
There are no onboard resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions.
9.4
SM Bus
System Management (SM) bus signals are connected to the Intel Apollo Lake SoC and the SM bus is not intended to be used by off-board
non-system management devices. For more information about this subject contact congatec technical support.