NOEL-ARTYA7-EX-QSG
December 2020, Version 1.2
7
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3. Board Configuration
This chapter describes boards items as used by the NOEL-ARTYA7-EX design.
Please see Arty A7 Reference Manual for a detailed legend of the reference designators.
3.1. Push buttons
•
BTN[0]
: Main reset to the FPGA design
•
BTN[1..]
: GPIO inputs [5..7]
3.2. Switches
•
SW[0..2]
DIP switch: GPIO inputs [0..2]
•
SW[3]
acts as select signal for the UART interface. When "ON" if selects the UART debug link. When
"OFF" it selects the console UART
3.3. LEDs
•
LED[0..3]
: Connected to GPIO0 outputs [16..19]
3.4. Connectors
•
J10
: USB JTAG interface via Digilent module with micro-B USB connector. See (Chapter 4).
• Ethernet PHY SGMII interface with RJ-45 connector. See (Chapter 4).
3.5. Memories
The NOEL-ARTYA7-EX has 256 MiB of SDRAM available on the on-chip bus.
3.6. Programming the bitstream
A Xilinx Vivado script to program the FPGA is provided with the bitfile distribution. The bitstream folder contains
several bistreams which represent different configurations of the processor (EX1,EX2, ecc.). Select one of the
bitstreams (described in [RD-1]. and follow the instructions below to program the FPGA:
To program the FPGA please follow these instructions:
1. Connect the PC and the board using a standard micro-USB cable into the connector
USB-JTAG J10
.
2. Make sure that Vivado is added to your path variables
3. Open a terminal in the downloaded folder and issue the following command to launch Vivado:
vivado -mode tcl -notrace -source doprog.tcl
4. To program the FPGA with the selected configuration, run in the Vivado console (in this case for EX1):
doprog EX1
5. Once the FPGA has been programmed, it is possible to connect to the board using GRMON, using the
command:
grmon -digilent
Please see (Chapter 4) for further information regarding GRMON and the available debug links.
Alternatively, the bitfile (
.bit
) can be programmed to the Digilent ARTY-A7 using the Vivado design suite
graphical interface. Start Vivado and select the menu item Flow -> Open Hardware Manager. Once the FPGA
has been programmed, remember to close the hardware manager before connecting with GRMON.
