GR740-UM-DS, Nov 2017, Version 1.7
405
www.cobham.com/gaisler
GR740
34
JTAG Debug Link with AHB Master Interface
34.1
Overview
The JTAG debug interface provides access to the Debug AHB bus through JTAG. The JTAG debug
interface implements a simple protocol which translates JTAG instructions to AHB transfers. Through
this link, a read or write transfer can be generated to any address on the AHB bus.
The JTAG debug interface will, together with all other cores on the Debug AHB bus, be gated off
when the Debug AHB bus is disabled via the external DSU_EN signal.
34.2
Operation
34.2.1 Transmission protocol
The JTAG Debug link decodes two JTAG instructions and implements two JTAG data registers: the
command/address register and data register. A read access is initiated by shifting in a command con-
sisting of read/write bit, AHB access size and AHB address into the command/address register. The
AHB read access is performed and data is ready to be shifted out of the data register. Write access is
performed by shifting in command, AHB size and AHB address into the command/data register fol-
lowed by shifting in write data into the data register. Sequential transfers can be performed by shifting
in command and address for the transfer start address and shifting in SEQ bit in data register for fol-
lowing accesses. The SEQ bit will increment the AHB address for the subsequent access. Sequential
transfers should not cross a 1 kB boundary. Sequential transfers are always word based.
Table 542.
JTAG debug link Command/Address register
34 33 32 31
0
W
SIZE
AHB ADDRESS
34
Write (W) - ‘0’ - read transfer, ‘1’ - write transfer
33 32
AHB transfer size - “00” - byte, “01” - half-word, “10” - word, “11”- reserved
31 30
AHB address
Table 543.
JTAG debug link Data register
32
31
0
SEQ
AHB DATA
32
Sequential transfer (SEQ) - If ‘1’ is shifted in this bit position when read data is shifted out or write
data shifted in, the subsequent transfer will be to next word address. When read out from the device,
this bit is ‘1’ if the AHB access has completed and ‘0’ otherwise.
31 30
AHB Data - AHB write/read data. For byte and half-word transfers data is aligned according to big-
endian order where data with address offset 0 data is placed in MSB bits.
Figure 45.
JTAG Debug link block diagram
AHB master interface
Debug AHB bus
JTAG Communication
Interface
JTAG TAP
Controller
TCK
TMS
TDI
TDO