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CMS80F731x Reference Manual
20.3 SPI Hardware Description
When an SPI transfer occurs, when one data pin moves out of one 8-bit character, the other data pin moves in the other 8-
bit character. The 8-bit shift register in the master device and another 8-bit shift register in the slave device are connected as a
cyclic 16-bit shift register, and when the transfer occurs, the distributed shift register is shifted by 8 bits, thus effectively swapping
the characters of the master slave.
The central element in the SPI system is the module containing the shift registers and the buffer for reading data. The
system is single buffer in the transmit direction and double buffer in the receive direction. This means that new data cannot be
written to the shifter until the previous data transfer is complete; However, the received data is transmitted to a parallel read data
buffer, so the shifter is free to receive a second serial character. As long as the first character is read out of the read data buffer
before the next serial character is ready for transmission, there is no overwrite. The SPI control block diagram is shown in the
following figure:
8-Bit Shift Register
Read Data Buffer
Divider
SPI Clock Logic
SPI Control Reg.
SPI Status Reg.
NSS Control Reg.
SPI Controller
MOSI
SPR
CPHA
CPOL
MISO
SCLK
NSS
The pins associated with SPI are: NSS, SCLK, MOSI, MISO.
The NSS output pins in master mode are used to select slave devices, and the NSS input pins in slave mode are used to
enable transmission.
In host mode, the SCLK pin is used as an SPI clock signal reference. When the host device initiates a transfer, eight clock
cycles are automatically generated on the SCLK pins.
