BAT32G1x9 user manual | Chapter 19 Universal serial communication unit
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Rev.1.02
19.3.5
Serial data register mn(SDRmn) (SCI0 i.e. m=0).
The SDR mn register is the data register (16-bit) that channel n sends and receives.
SDR00, bit8 to 0 of SDR01 (9 bits lower) or SDR02, SDR03 Bit7 to 0 (low 8 bits) is used as a transmit and
receive buffer register, bit15 to 9 (high 7 bits) is used as a crossover setting register for the operating clock (f
MCK
).
If the CCSmn position of the serial mode register mn (SMRmn) is "0", the bit15 to 9 of the SDRmn register
is used The divider clock of the operating clock (7 bits high) is used as the transmission clock.
If the CCSmn position is "1", the bit15 to 9 (height 7) of SDR00 and SDR01 must be placed bit) to
"0000000B". The input clock of the SCLKp pin, f
SCLK
(slave transmission in SSPI mode), is the transmit
clock.
The low 8 bits or 9 bits low of the SDRmn registers are used as transmit and receive buffer registers.
When receiving data, save the parallel data converted by the shift register to 8 bits low or 9 bits low; When
sending data, the transmit data transmitted to the shift register is set to 8 bits low or 9 bits low.
SDRmn registers can be read and written in 16-bit increments. However, the high 7 bits can only be read
and written when the run stops (SEmn=0). In operation (SEmn=1) only the low 8 bits or 9 bits lower of the
SDRmn register can be written, and the high of the SDRmn register is 7 The read value of the bit is always
"0".
After generating the reset signal, the value of the SDRmn register changes to "0000H".
Figure 19-8
serial data register mn (SDRmn).
After reset: 0000H
R/W
SDR00
case
SDR00
case
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDRmn
After reset: 0000H
R/W
SDR02
case
SDR02
case
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDRmn
0
SDRmn[15:9]
Run the transmit clock setting for clock
division
0
0
0
0
0
0
0
f
MCK
/2
0
0
0
0
0
0
1
f
MCK
/4
0
0
0
0
0
1
0
f
MCK
/6
0
0
0
0
0
1
1
f
MCK
/8
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
0
f
MCK
/254
1
1
1
1
1
1
1
f
MCK
/256
Note 1
The
bit8
of
the SDR02
and
SDR03
registers
must be
set to
"0".
2. When using
UART, it is forbidden to
set
SDRmn [15:9]
to
"0000000B"
and
"0000001B".
3. When using Simple
I2C, it is forbidden to set SDRmn [15:9]
to
"0000000B", and the setting value of SDRmn [15:9]
must be greater than or equal
“0000001B”
。
4. When the operation stops (SEmn=0), it is forbidden to rewrite SDRmn [7:0] through the 8-bit memory operation
instruction (otherwise, SDRmn [15:9] is all cleared "0").
Note 1 For the function of the SDRmn register low 8 bit or low 9 bit, refer to "19.2 19.2The
universal serial communication unit
2.m: unit number (m=0) n: channel number (n=0~3).
