BAT32G1x9 user manual | Chapter 10 Timer M
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Rev.1.02
10.7.6
External clock TMCLK
The pulse width of the external clock input to the TMCLK pin must be at least 3 timer M operating clock
cycles.
Reset synchronous PWM mode
•
When this mode is used for motor control, it must be used under the condition of OLS0=OLS1.
• To set the reset sync PWM mode, you must follow the steps below
to set it up. [Change Step].
(1) Place the TSTART0 position of the TMSTR register "0" (stop count).
(2) Place the CMD1 bit and CMD0 position "00B" of the TMFCR register (timer mode, PWM mode,
and PWM3 mode).
(3) Place CMD1 bit and CMD0 position "01B" (reset synchronous PWM mode).
(4) Reset the other associated registers for timer M.
10.7.7
Complementary PWM mode
•
When this mode is used for motor control, it must be used under the condition of OLS0=OLS1.
•
To change the CMD0 bits and CMD1 bits of the TMFCR registers, you must follow the steps below
to make the changes.
[Change step: when set to complementary PWM mode (including resetting), or change the data
transfer timing of buffer registers to General Purpose registers in complementary PWM mode].
(1) Both the TSTART0 bits and the TSTART1 bits of the TMSTR register are set to "0" (stop count).
(2) Place the CMD1 bit and CMD0 position "00B" of the TMFCR register (timer mode, PWM mode,
and PWM3 mode).
(3) Place CMD1 bit and CMD0 at "10B" or "11B" (complementary PWM mode).
(4) Reset the other associated registers for timer M.
[Change Step: Case of Discontinuation of Complementary PWM Mode].
(1) Both the TSTART0 bits and the TSTART1 bits of the TMSTR register are set to "0" (stop count).
(2) Place cmD1 bit and CMD0 position "00B" (timer mode, PWM mode, and PWM3 mode).
•
TMGRA0, TMGRB0, TMGRA1, TMGRB1 registers cannot be written during operation.
To change the PWM waveform, the write values of the TBMGRD0, TMGRC1, and TMGRD1
registers must be transmitted to TMGRB0 via buffer operation TMGRA1, TMGRB1 registers.
However, when writing TMGRD0, TMGRC1, and TMGRD1, you must first change the TMBFD0 bit,
TMBFC1 Bits and TMBFD1 position "0" (General Purpose registers) and then write data to these registers.
Thereafter, TMBFD 0 bits, TMBFC1 bits, and TMBFD1 positions "1" (buffer registers) can be changed.
The PWM period cannot be changed.
•
Assuming that the setting value of the TMGRA0 register is m, the TM0 register performs m
–1 m
when changing from an increasing count to a decrement count
Count of m+1
m
m
–1.
When performing an increment count of m
m+1, the IMFA bit of the TMSRi register becomes "1".
When the CMD1 bit and CMD0 bits of the TMFCR register are "11B" (complementary PWM mode, at
TM0 When the buffer data is transmitted when matching the TMGRA0 register), the contents of the
buffer register (TMGRD0, TMGRC1, TMGRD1) are transmitted to the general-purpose register
(TMGRD0, TMGRD1, TMGRD1). TMGRB0, TMGRA1, TMGRB1)
。
When performing a decrement count of m+1
m
m
–1, the IMFA bits do not change and data is not
transmitted to registers such as TMGRA0.
