BAT32G1x9 user manual | Chapter 5 Hardware divider
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Rev.1.02
Chapter 5 Hardware divider
Hardware dividers are specific-built hardware to support high-performance computing. The hardware
divider is a 32-bit signed integer divider that outputs a 32-bit signed quotient and remainder result.
5.1 Features
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32-bit signed (complement of 2) integer division calculations
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32 bits signed dividend and 32 bits signed divisors
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32-bit signed quotient and 32-bit signed remainder output
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Writing divisor register automatically triggers the division calculation
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Divided by 0 warning flag
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Indicates the BUSY flag in the operation
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There is an interrupt request for calculation completion
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Each calculation takes 4 or 8 CPU clock cycles
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It takes 4 CPU clock cycles at double speed
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It takes 8 CPU clock cycles in the non-double speed state
5.2 Feature description
When using a hardware divider, you need to set the DIVIDEND register (DIVIDEND) first and then the
DIVISOR, because a write to the divisor register automatically triggers the division calculation. By querying
the STATUS BIT of the BUZZ or by using an interrupt at the end of the calculation, you can know when the
settlement ended. The calculation results can be read through the quotient (QUOTIENT) and remainder
(REMAINDER) registers.
Note: Do not write dividend or divisor registers during calculation, and do not read quotient or remainder
registers, otherwise the result is unpredictable.
5.3 Registers for the hardware divider
The registers for the hardware divider are as follows:
Register base address: DIV_BASE = 4008_0000H;
Register name
Register description
R/W Reset value
Register address
DIVIDEND
The divisor register
R/W 0000_0000H
D00H
DIVISOR
Dividend register
R/W 0000_0000H
D04H
QUOTIENT
Quotient register
R
0000_0000H
D08H
REMAINDER
Remainder register
R
0000_0000H
D0CH
STATUS
Status register
R
0000_0000H
D10H
R: read only, W: write only, R/W: both read and write
