CMT2300A
Rev 1.0 | Page27/46
www.cmostek.com
5. Chip Operation
5.1 SPI Interface
The chip communicates with the outside through the 4-wire SPI interface. The CSB is the active-lowchip select signal for
accessing to the registers. The FCSB is the active-low select signal for accessing to the FIFO. They cannot be set to low at the
same time. The SCLK is the serial clock.Its highest speed is 5MHz.The chip itself and the external MCU send the data at the
falling edge of SCLK and capture the data at the rising edge of SCLK. The SDA is a bidirectional pin for input and output data.
The address and data are transferred starting from the MSB.
When accessing to the register, CSB is pulled low. A R/W bit is sent first, followed by a 7-bit register address. After the external
MCU pulls down the CSB, it must wait for at least half a SCL cycle, and then send the R/W bit. After the MCU sends out the last
falling edge of SCLK, it must wait for at least half a SCLK cycle, and then pull the CSB high.
To be noticed, when reading a register, MCU and CMT2300A will have to switch the direction of their IO (SDIO) between the
address bit 0 and the data bit 7. It is required that the MCU switches the IO to input mode before send out the falling edge of the
SCLK; CMT2300A should switch the IO to output mode after it has seen the falling edge of the SCLK. This avoids data
contention of the SDIO (both of the MCU and CMT2300A set the SDIO to output mode at the same time), which would cause
unexpected electrical problem.
SCLK
CSB
SDIO
X
0
1
2
3
4
5
6
7
X
register address
register read data
0
1
2
3
4
5
6
7
r/w = 1
FCSB
> 0.5 SCLK cycle
> 0.5 SCLK cycle
Figure 9. SPI read register timing
SCLK
CSB
SDIO
X
X
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
register address
register write data
FCSB
r/w = 0
> 0.5 SCLK cycle
> 0.5 SCLK cycle
Figure 10. SPI write register timing
5.2 FIFO
CMT2300A provides two separated 32-byte FIFO by default. They are used for RX and TX, respectively. Users can also set
