Rev1.0a | 25/50
CMT2300A
The first case is a very short and sudden decrease of VDD. The POR triggering condition is, VDD dramatically decreases by 0.9V
+/- 20% (e.g. 0.72V
– 1.08V) within less than 2 us. To be noticed, it detects a decreasing amplitude of the VDD, not the absolute
value of VDD as shown in the below figure.
VDD
0.9 V x (1 +/- 20%)
POR
< 0.2 us
Figure 5. Sudden Decrease of VDD lead to Generation of POR
The second case is, a slow decrease of the VDD. The POR triggering condition is, VDD decreases to 1.45V +/- 20% (e.g. 1.16V
– 1.74V) within a time more than or equal to 2 us. To be noticed, it detects an absolute value of VDD, not a decreasing amplitude.
VDD
1.45 V x (1 +/- 20%)
POR
> 0.2 us
Figure 6. Slow Decrease of VDD lead to Generation of POR
4.3.2 Crystal Oscillator
The crystal oscillator provides a reference clock for the phase locked loop as well as a system clock for the digital circuits. The
value of load capacitance depends on the crystal specified CL parameters. The total load capacitance between XI and XO should
be
equal to CL, in order to make the crystal accurately oscillate at 26 MHz.
C15 and C16 are the load capacitances at both ends of the crystal. Cpar is the parasitic capacitance on the PCB. Each crystal pin
has 5pF internal parasitic capacitance, together is equivalent to 2.5pF. The equivalent series resistance of the crystal must be within
the specifications so that the crystal can have a reliable vibration. Also, an external signal source can be connected to the XI pin to
replace the conventional crystal. The recommended peak value of this clock signal is from 300mV to 700mV. The clock is coupled to XI
pin via a blocking capacitor.
