
Evaluation Kit for CMX7x6x
PE0601-xxxx
©
2011 CML Microsystems Plc
20
UM0601/2
5
Circuit Schematics and Board Layouts
For clarity, circuit schematics are available as separate high-resolution files. These can be
obtained via the CML website.
R66
+
C7
7
R29
R16
R25
R26
C7
9
R7
1
R5
0
R11
R4
9
C5
9
C69
C81
R77
R56
C5
3
C5
0
R5
1
R5
4
C47
R47
C1
C6
R12
R4
1
C3
C4
8
C5
4
C3
9
C56
R22
C1
3
TP12
R5
8 R64
R27
C2
2
+
C2
5
D6
L1
D2
R70
C2
1
TP2
3
R72
TP24
R6
0
C7
0
R6
3
C5
8
R32
R15
D1
C4
R
5
9
TP27
R76
R7
8
R9
TP26
R8
TP20
R3
0
C3
8
R3
4
C61
R3
TP
3
R36
R52
C4
2
R2
R37
R3
5
C4
1
R4
2
C14
C62
R45
R5
R4
U17
D5
R
5
3
C4
0
R3
9
R4
0
C1
2
D7
+
C2
6
U12
TP22
TP6
TP7
C80
R74
+4V
TP21
C37
+
C24
C11
C19
C20
R17
C6
0
C46
R46
R6
1
C2
C5
1
C5
2
C7
R13
R4
8
R5
7
C4
9
R28
C72
C74
+
C65
TP5
SYSCLK2
R62
R6
R33
GNDA
TP11
C5
5
X1
R1
9
R67
C9
R14
U6
TP2
C32
TP13
-V
TP14
+V
C36
C78
R73
SPKR3V3
TP17
+
C31
TP15
AVDD
C27
U3
+
C33
SW1
+
C2
9
TP16
DVDD
C23
JP9
D3
JP8
+
C18
R69
R68
Q_OUT
J21
TP25
R7
5
C8
2
C43
R7
C44
R43
C5
7
R1
0
C7
6
JP1
4
U2
R65
R2
4
TP10
TP9
GNDD
R1
R3
1
VR1
Q_IN
J18
R44
C73
C75
C17
C16
C71
U4
J5
C1
0
R20
R5
5
+
C3
4
J16
2
1
9
10
J8
A
udi
o
U7
U16
9
2
1
10
A
u
x A
nalogue
J1
3
VR2
X2
U5
U13
R1
8
2
9 10
1
J6
1
2
19
20
J14
TP8
R38
U18
U8
+
C35
EXT_VCORE
TP19
JP13
BOOTEN2
JP2
TP4
SYSCLK1
TP1
C15
+
C5
-4V
TP18
I_IN
J17
I_OUT
J20
JP1
1
2
1
10
9
J19
2
1
10
9
J24
+
C6
8
U10
L2
+
C28
U9
BOOTEN1
JP1
U1
R23
R21
U15
U14
J10
Radi
o I/
fa
ce
J2
2
J1
1
U11
19
1
2
20
GPIO
J7
0V
Mod
3
2
1
4
7
6
5
9
8
PE0601-
Serial Number
123.0
138.0
1
19
20
2
PE0002 C-BUS
1
2
6
5
J23
1
2
20 19
C-
BU
S
M
as
ter
Figure 3 – PCB Layout: Top