CML Microcircuits PE0403, Руководство пользователя

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Evaluation Kit for CMX724x/CMX734x PE0403

2014 CML Microsystems Plc 9 um0403/1
4.
Signal Lists
Table 1 Signal List
CONNECTOR PINOUT
Connector
Ref.
Connector
Pin No.
Signal
Name
Signal
Type
Description
J1
TIP
SPKR O/P AUDIO
RING
- (O/P) (dependent on the setting of JP4, see 6.1.6)
SLEEVE
GNDA PWR Analogue ground.
J4 - CLK EXT I/P External input option for CMX7240/CMX7340
clock.
J6 1,4,5,6,
9,10,18 - N/C Do not make any connection to these pins
2 GPIO1 BI General purpose I/O pin.
3 GPIO2 BI General purpose I/O pin.
7 GPIOA BI General purpose I/O pin.
8 GPIOB BI General purpose I/O pin.
11 SYSCLK2 O/P CMX7240/CMX7340 system clock 2 output.
12 SYSCLK1 O/P CMX7240/CMX7340 system clock 1 output.
13 MOSI O/P SSP Master output, slave input.
14 SSOUT/
FSO
BI SSP Frame sync.
15 MISO I/P SSP Master input, slave output.
16 EPSCSN O/P EEPROM Chip Select
17 SSPCLK BI SSP Clock.
19, 20 GNDD PWR Digital supply ground.
J7 3, 5, 7, 9,
15 to 20
- N/C Do not make any connection to these pins
1 RESET I/P CMX7240/CMX7340 Hardware Reset Pin
2 CSN I/P Chip select. Connects to host

C.
4 CDATA I/P
Serial Data input. Connects to host

C.
6 SCLK I/P Serial clock input. Connects to host

C.
8 RDATA O/P Serial data output. Connects to host

C.