Schematic Diagrams
RS880M-SPMEM/ STRAPS 3/4 B - 9
B.Sch
e
m
a
tic D
iag
rams
RS880M-SPMEM/ STRAPS 3/4
R171
* 3K_1%_04
R173
3K_1%_04
R178
*3K_1%_0
4
R175
*3K_1%_0
4
R177
3K_1%_04
S
B
D
_
ME
M/
D
V
O
_
I/
F
PAR 4 OF 6
U2
5D
RS880M A11 HF MVD
MEM_A0(NC)
AB1
2
MEM_A1(NC)
AE1
6
MEM_A2(NC)
V1
1
MEM_A3(NC)
AE1
5
MEM_A4(NC)
AA1
2
MEM_A5(NC)
AB1
6
MEM_A6(NC)
AB1
4
MEM_A7(NC)
AD1
4
MEM_A8(NC)
AD1
3
MEM_A9(NC)
AD1
5
MEM_A10(NC)
AC1
6
MEM_A11(NC)
AE1
3
MEM_A12(NC)
AC1
4
MEM_A13(NC)
Y1
4
MEM_BA0(NC)
AD1
6
MEM_BA1(NC)
AE1
7
MEM_BA2(NC)
AD1
7
MEM_RASb(NC)
W1
2
MEM_CASb(NC)
Y1
2
MEM_WEb( NC)
AD1
8
MEM_CSb(NC)
AB1
3
MEM_CKE(NC)
AB1
8
MEM_O
DT(NC)
V1
4
MEM_CKP(NC)
V1
5
MEM_CKN( NC)
W1
4
MEM_DM
0(NC)
W17
M
EM
_DM1/DVO_D8(NC)
AE19
M
EM
_DQS0P/DVO_IDCKP(NC)
Y17
MEM_
DQS0N/DVO_IDCKN(NC)
W18
M
EM
_DQS1P(NC)
AD2
0
MEM_DQ
S1
N(NC)
AE21
M
EM
_DQ0/DVO_
VSYNC(NC)
AA18
MEM_DQ
1/DVO_HSYNC(NC)
AA20
MEM_DQ
2/ DVO
_DE(NC)
AA19
M
EM
_DQ3/DVO_D0(NC)
Y19
MEM_DQ
4(NC)
V17
M
EM
_DQ5/DVO_D1(NC)
AA17
M
EM
_DQ6/DVO_D2(NC)
AA15
M
EM
_DQ7/DVO_D4(NC)
Y15
M
EM
_DQ8/DVO_D3(NC)
AC2
0
M
EM
_DQ9/DVO_D5(NC)
AD1
9
MEM_
DQ10/DVO_D6(NC)
AE22
MEM_
DQ11/DVO_D7(NC)
AC1
8
MEM_DQ
12(NC)
AB20
MEM_
DQ13/DVO_D9(NC)
AD2
2
MEM_DQ14/DVO_D10(NC)
AC2
2
MEM_DQ15/DVO_D11(NC)
AD2
1
MEM_COMPP( NC)
AE1
2
MEM_COMPN(NC)
AD1
2
MEM_VREF(NC)
AE18
IO
PLLVDD18(NC)
AE23
IOPLLVSS(NC)
AD2
3
I O
PLL
VDD(NC)
AE24
3.3VS
3.3VS
1
. 1VS
1
. 8VS
A_RST#
7,22,33
STRAP_DEBUG_BUS_GPIO_ENABLEb
Se le cts Lo ad in g of STRAPS fr om EPR OM
1 : B yp a s s t he lo adi ng o f EEPR OM s tra p s an d u se H ar d ware D efa ult Va lu es
0 : I 2C Ma s te r c an loa d st ra p value s fro m E EPROM if co nne cted , o r u s e
d e fa ult val ues if n o t con ne ct ed
En able s the Tes t D eb u g Bus u s ing G PIO.
RS8 80M
1 Di sab le
0 En ab le
RS880M: Enables Side por t memor y
DFT_GPIO1: LOAD_EEPROM_STRAPS
R S8 80 M: HSYNC #
Se le cts if Memory S IDE P ORT is availa bl e o r no t
1 = Me mo r y Sid e po rt Not a va ila ble
0 = Me mo r y Sid e po rt ava ila ble
R egis te r Re ad ba ck of s tr ap :
N B_ CL KCFG: CLK_ TOP_SPAR E_D[1]
VSYNC#
7,21
HSYNC#
7,21
R460
0_04
D30
*RB751V
A
C
SUS_STAT#
7,23
Sheet 8 of 48
CPU 7/7
(RESERVED)
Содержание W150DAQ
Страница 1: ...W150DAQ SERVICE MANUAL ...
Страница 2: ......
Страница 3: ...Preface I Preface Notebook Computer W150DAQ Service Manual ...
Страница 24: ...Introduction 1 12 Mainboard Overview Bottom Connectors 1 Introduction ...
Страница 43: ...Top A 3 A Part Lists Top 灰色 黑色 Figure A 1 Top with Finger print ...
Страница 44: ...A 4 Bottom A Part Lists Bottom Figure 2 Bottom ...
Страница 45: ...SATA BLU RAY COMBO A 5 A Part Lists SATA BLU RAY COMBO Figure A 3 SATA BLU RAY COMBO 非耐落 志精 ...
Страница 46: ...A 6 SATA DVD SUPER MULTI A Part Lists SATA DVD SUPER MULTI 非耐落 志精 太 乙 Figure A 4 DVD Dual Drive ...
Страница 47: ...LCD A 7 A Part Lists LCD Figure A 5 LCD 非耐落 銘板 一般漆 W150HNQ ...
Страница 48: ...A 8 LCD A Part Lists ...
Страница 93: ...Schematic Diagrams AUDIO Board B 45 B Schematic Diagrams AUDIO Board Sheet 44 of 48 AUDIO Board ...
Страница 98: ...Schematic Diagrams B 50 B Schematic Diagrams ...
Страница 101: ...www s manuals com ...