50
DS245F4
CS8420
11.5
Block-Mode U-Data D-to-E Buffer Transfers
When Fsi
≠
Fso, Block-Mode U-data transfers from the D buffer to the E buffer are not synchronous to the
input clock domain. D-to-E buffer transfers can always be detected by the activation of the DETU bit (bit 3
in register 08h) when Fsi
≠
Fso or Fsi
=
Fso. IEC Consumer B mode, serial U-data output, and the Q-
channel subcode bytes (registers 14h - 1Dh) are unaffected by the input/output sample rate relationship.
11.6
ID Code and Revision Code
The CS8420 has a register that contains a 4-bit code to indicate that the addressed device is a CS8420.
This is useful when other CS84xx family members are resident in the same system, allowing common soft-
ware modules.
The CS8420 4-bit revision code is also available. This allows the software driver for the CS8420 to identify
which revision of the device is in a particular system, and modify its behavior accordingly. To allow for future
revisions, it is strongly recommend that the revision code is read into a variable area within the microcon-
troller, and used wherever appropriate as revision details become known.
11.7
Power Supply, Grounding, and PCB layout
For most applications, the CS8420 can be operated from a 5V supply, following normal supply de-
coupling practice (see
Figure 5. “Recommended Connection Diagram for Software Mode” on page 12
). For
applications where the recovered input clock, output on the RMCK pin, is required to be low-jitter, then use
a separate, quiet, 5V supply for VA+, decoupled to AGND. In addition, a separate region of analog
ground plane around the FILT, AGND, VA+, RXP and RXN pins is recommended.
The VD+ supply should be well-decoupled with a 0.1
μ
F capacitor to DGND to minimize AES3 transmitter
induced transients.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Make sure decoupling capacitors are mounted on the same side of the board
as the CS8420, to minimize via inductance effects. All decoupling capacitors should be as close to the
CS8420 as possible.
11.8
Synchronization of Multiple CS8420s
The serial audio output ports of multiple CS8420s can be synchronized by sharing the same master clock,
OSCLK, OLRCK, and RST line and ensuring that all devices leave the reset state on the same master clock
falling edge. Either all the ports need to be in Slave mode, or one can be set as a master.
The AES3 transmitters may be synchronized by sharing the same master clock, TCBL, and RST signals,
and ensuring all devices leave the reset state on the same master clock falling edge. The TCBL pin is used
to synchronize multiple CS8420 AES3 transmitters at the channel status block boundaries. One CS8420
must have its TCBL set to master; the others must be set to slave TCBL. Alternatively, TCBL can be derived
from some external logic, in which case all the CS8420 devices should be set to slave TCBL.
11.9
Extended Range Sample Rate Conversion
For handling sampling rate conversion ratios greater than 3:1 or less than 1:3, the user can use a cascade
of two devices. The product of the conversion ratio of the two devices should equal the target conversion
ratio.
