DS633F1
67
CS44600
er-down state by setting the PDN bit in the register
“Clock Configuration and Power Control (address 02h)”
on page 51
to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.29.4
Channel A3 Output Configuration (A3_OUT_CNFG)
Default = 0
0 - pwm outputs for channel A3 are configured for half-bridge operation
1 - pwm outputs for channel A3 are configured for full-bridge operation
Function:
Identifies the output configuration. The value selected for this bit is applicable to the outputs for only chan-
nel A3. This parameter can only be changed when all modulators and associated logic are in the power
down state by setting the PDN bit in the register
“Clock Configuration and Power Control (address 02h)”
on page 51
to a ‘1’b. Attempts to write this register while the PDN is not set will be ignored.
7.29.5
Channel B3 Output Configuration (B3_OUT_CNFG)
Default = 0
0 - pwm outputs for channel B3 are configured for half-bridge operation
1 - pwm outputs for channel B3 are configured for full-bridge operation
Function:
Identifies the output configuration. The value selected for this bit is applicable to the outputs for only chan-
nel B3. This parameter can only be changed when all modulators and associated logic are in the power-
down state by setting the PDN bit in the register
“Clock Configuration and Power Control (address 02h)”
on page 51
to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.30
PWM Minimum Pulse Width Register (address 32h)
7.30.1
Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-)
Default = 0
0 - PWM minus (“-”) differential signal is operational when PWM channel is configured for half-bridge.
1 - PWM minus (“-”) differential signal is disabled when PWM channel is configured for half-bridge.
Function:
Determines if the PWM minus (“-”) differential signal is disabled when the particular PWM channel is con-
figured for half-bridge operation. This bit is ignored for channels configured for full-bridge operation. The
value selected for this bit is applicable to the outputs for all channels configured for half-bridge operation.
This parameter can only be changed when all modulators and associated logic are in the power-down
state by setting the PDN bit in the register
“Clock Configuration and Power Control (address 02h)” on
page 51
to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.30.2
Minimum PWM Output Pulse Settings (MIN_PULSE[4:0])
Default = 00000
Function:
The PWM Minimum Pulse registers allow settings for the minimum allowable pulse width on each of the
PWMOUT differential signal pairs, P and PWMOUTxx-. The value selected in this register is
applicable to all PWM channels. The effective minimum pulse is calculated by multiplying the register val-
ue by the period of the PWM_MCLK. This parameter can only be changed when all modulators and as-
sociated logic are in the power-down state by setting the PDN bit in the register
“Clock Configuration and
7
6
5
4
3
2
1
0
DISABLE_PWMOUTXX- RESERVED
RESERVED MIN_PULSE4 MIN_PULSE3
MIN_PULSE2
MIN_PULSE1
MIN_PULSE0
