Cirrus Logic CS4399, Руководство пользователя

Страница: 19 / 111

DS1113F1 19
CS4399
3 Characteristics and Specifications
4.TDM interface timing
(shown with xSP_FSD = 010, xSP_LCHI = 1)
5.Applies to Master and Slave Modes, unless specified otherwise.
6.Maximum LRCK duty cycle is equal to frame length, in SCLK periods, minus 1. Maximum duty cycle occurs when LRCK high (xSP_LCHI) is set to
768 SCLK periods and LRCK period (xSP_LCPR) is set to 769 SCLK periods.
7.Data may be latched/launched on either the rising or falling edge of SCLK.
8.SCLK duty cycle in Master Mode depends on Master Mode clock configuration, and can vary by up to 1 MCLK
EXT
period.
9.Data is latched/launched on the rising or falling edge of SCLK as determined by xSP_SCPOL_OUT, xSP_SCPOL_IN, and xSP_FSD bits. See the
SCLK launching specs in Table 3-15 .
Table 3-16. DSD Switching Characteristic
Test conditions (unless specified otherwise): Fig. 2-1 shows CS4399 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;
parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =
1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; T
A
= +25°C; C
L
= 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at V
OL
and V
OH
thresholds (see Table 3-8 ).
Parameter 1,2
1.Serial audio input interface timing
2.Phase modulation mode serial audio input interface timing
Symbol Minimum Typical Maximum Units
DSDCLK duty cycle — 40 — 60 %
DSDCLK pulse width low t
SCLKL
80 — — ns
DSDCLK pulse width high t
SCLKH
80 — — ns
DSDCLK frequency (64× oversampled)
(128× oversampled)
— 1.024
2.048 2.8224
5.6448 f
MCLK_INT
/8
f
MCLK_INT
/4
MHz
MHz
DSDA/DSDB valid to DSDCLK rising setup time t
SDLRS
20 — — ns
DSDCLK rising to DSDA or DSDB hold time t
SDH
20 — — ns
DSD clock to data transition (Phase Modulation Mode) t
DPM
–20 — 20 ns
Table 3-17. I 2 C Slave Port Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to
ground; VL = 1.8 V; inputs: Logic 0 = GNDA = 0 V, Logic 1 = VL; T
A
= +25°C; SDA load capacitance equal to maximum value of C
B
= 400 pF; minimum
SDA pull-up resistance, R
P(min)
. 1 Table 3-1 describes some parameters in detail. All specifications are valid for the signals at the pins of the CS4399 with
the specified load capacitance.
Parameter 2 Symbol 3 Minimum Maximum Units
SCL clock frequency f
SCL
— 1000 kHz
Clock low time t
LOW
500 — ns
Clock high time t
HIGH
260 — ns
Start condition hold time (before first clock pulse) t
HDST
260 — ns
Setup time for repeated start t
SUST
260 — ns
SCLK
SDIN
t
SU:SDI
t
H: SDI
LRCK/FSYNC
t
D:CLK-FSYNC
1/f
SCLK
Don’t Care
Frame location 0 Frame location N -1
1/Fs
...
...
...
f
SCLK
= N · Fs
t
SU :FSYNC
t
H: FSYNC
t
HI:FSYNC
t
LO:SCLK
t
HI:SCLK
DSDCLK
DSDA,
DSDB
t
SDLRS
t
SDH
t
SCLKL
t
SCLKH
DSDCLK
(128
•
Fs)
DSDCLK
(64
•
Fs)
DSDA,
DSDB
t
DPM
t
DPM