chromasens allPIXA, Руководство пользователя

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CD40047_R04_allPIXA_User-Manual.docx 24
4.6 Image processing
Image processing in the allPIXA camera is analog and digital. The following block diagram
illustrates the internal processes.
Analog / digital image processing
The power block provides all required voltages which are available for the camera electronic
components from the supplied 24 V DC.
The image is acquired by the CCD sensor and initially processed in analog mode, followed by
an analog/digital converter. The digital image processing is done in the FPGA.
The image data generated by the allPIXA camera are converted in the video interface to the
Camera Link standard and then sent to the frame grabber.
Figure 8: Process of the allPIXA camera image processing (block diagram)
The CCD sensor is read out by using a shift register. The CDS (correlated double-sampling)
process filters (extracts) the intended signal information from the received signals. After that
process, the global amplification (gain) and offset values (black-level offset) are adjusted. In the
last step, the analog information is converted to digital 14-bit values to forward these to the
digital processing unit.
Figure 9: Analog process of the allPIXA camera (block diagram)
CDS Gain Offset 14 Bit ADC
CDS Gain Offset 14 Bit ADC
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CDS Gain Offset 14 Bit ADC
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