Chromasens CD40127_R02 allPIXA_pro_User Manual.docx
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4.5 Image processing
Image processing in the allPIXA pro camera is analog and digital. The following block diagram
illustrates the internal processes.
4.5.1 Analog / digital image processing
The power block provides all required voltages which are available for the camera electronic
components from the supplied 24 V DC.
The image is acquired by the CCD sensor and initially processed in analog mode, followed by
an analog/digital converter. The digital image processing is done in the FPGA.
The image data generated by the allPIXA pro camera is converted in the video interface to the
Camera Link standard and then sent to the frame grabber.
Figure 15: Process of the allPIXA pro camera image processing (block diagram)
The CCD sensor is read out by use of a shift register. The CDS (correlated double sampling)
process filters (extracts) the intended signal information from the received signals. After that
process, the global amplification (gain) and offset values (black-level offset) are adjusted. In
the last step, the analog information is converted to digital 14 bit values to forward these to the
digital processing unit.
Figure 16: Analog process of the allPIXA pro camera (block diagram)
CDS
Gain
Offset
14 Bit ADC
CDS
Gain
Offset
14 Bit ADC
from microcontroller
to
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ig
ita
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ro
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ODD
CDS
Gain
Offset
14 Bit ADC
CDS
Gain
Offset
14 Bit ADC
from microcontroller
to
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ig
ita
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ro
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ss
in
g
ODD
Fr
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n
t T
ap
Rea
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ap
C
C
D
S
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EVEN
Coarse
Gain
Coarse
Gain
Coarse
Gain
Coarse
Gain
(1)
(2)
