Changhong Electric PT4216, Руководство по обслуживанию, Страница: 20 / 62

20
43,51,58,68,75,83
93
2 TDO
Test Data Output for Boundary Scan Test
(2)
3 TDI Test Data Input for Boundary Scan Test (with internal pull-up)
(2)
4 XTOUT
crystal oscillator output signal, auxiliary signal
6 XTALO
7 XTALI 24.576 (32.11) MHz crystal oscillator output; not connected if XTALI is driven
by an external single-ended oscillator.
Input terminal for 24.576 (32.11) MHz crystal oscillator or connection of external oscillator
with TTL compatible square wave clock signal.
6 VXDD Crystal oscillator power supply
10,12,14,16 AI21~AI24 Analog signal input
13 AI2D
19 AI1D
differential input for ADC channel 2 (pins AI24, AI23, AI22, AI21)
differential input for ADC channel 1 (pins AI12, AI11)
20 AI11
18 AI12 analog input 11
analog input 12
5,9,15,21,24,26,38
50,63,76,88,100 AGND
VSS ground
22 AOUT
Analog test output (do not connect)
27 CE Chip Enable or RESET input (with internal pull up)
28 LLC
29 LLC2
line-locked system clock output (27 MHz nominal), for backward compatibility,
do not use for new applications
line locked clock/2 output (13.5 MHz nominal) for backward compatibility, do
not use for new applications
30 RESON RESet Output Not signal
31 SCL
IIC serial clock line (with inactive output path)
32 SDA
IIC serial data line
34 RTS0
35 RTS1
real time status or sync information, controlled by subaddr. “11h and 12h”
RTS1 35 O real time status or sync information, controlled by subaddr. “11h and 12h”
36 RTCO Real time control output
37 AMCLK Audio master clock output
39 ASCLK Audio serial clock output
40 ALRCLK Audio lift/right clock output
41 AMXCLK Audio master external clock input
42 ITRDY Target ready input, image port(with internal pull up)
45 ICLK clock output signal for image-port, LCLK of LPB image port mode, or optional
asynchron. backend clock input
46 IDQ output data qualifier for image port
(optional: gated clock output)
47 ITRI
image-port output control signal, effects all I-port pins incl. ICLK, enable and active
polarity is under software control (bits IPE in subaddr. “87”) output path used for
Testing
:
scan output
48 IGP0
49 IGP1 general purpose output signal 0; image-port (controlled by subaddr. “84”,”85”)
general purpose output signal 1; image-port (controlled by subaddr. “84”,”85”),
same functions as IGP0
52 IGPV multi purpose vertical reference output signal; image-port
(controlled by subaddr. “84”,”85”)
53 IGPH multi purpose horizontal reference output signal; image-port
(controlled by subaddr. “84”,”85”)
54~57,59~62 IPD0~IPD7 image port data output
64~67,69~72 HPD0~HPD7
Host port data I/O, carries UV chrominance information in 16 bit video I/O modes
80 XTRI
X-port output control signal, effects all X-port pins (XPD[7:0], XRH, XRV, XDQ
and XCLK) enable and active polarity is under software control (bits XPE in subaddr.
“83”)
81,82,84,85,
89,90,86,87 XPD0~XPD7 expansion-port data
expansion-port data