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Carbon Cortex-M3 Model 

User Guide for 

SoC Designer Plus

Carbon Model Version 4.0.0

For the ARM Cortex-M3 Processor

Silicon Version: r2p0

The Trusted Path to 

Accuracy

 

™

The information contained in this document is confidential information of Carbon Design Systems, Inc.,

and may not be duplicated or disclosed to unauthorized and/or third parties.

Содержание Cortex-M3

Страница 1: ...ersion 4 0 0 For the ARM Cortex M3 Processor Silicon Version r2p0 The Trusted Path to Accuracy The information contained in this document is confidential information of Carbon Design Systems Inc and m...

Страница 2: ...ithout limitation those resulting from loss of use data or profits whether or not advised of the possibility of damage and on any theory of liability arising out of or in connection with the use or pe...

Страница 3: ...EST Carbon Design Systems Inc 125 Nagog Park Acton MA 01720 Voice 1 978 264 7399 Asia 81 3 5524 1288 Fax 1 978 264 9990 Email support carbondesignsystems com Web www carbondesignsystems com Voice mail...

Страница 4: ...Carbon Design Systems Inc Confidential...

Страница 5: ...Hardware 1 4 Adding and Configuring the SoC Designer Plus Component 1 4 Carbon SoC Designer Plus Component Files 1 4 Adding the Carbon Model to the Component Library 1 5 Adding the Component to the S...

Страница 6: ...vi Contents Carbon Design Systems Inc Confidential...

Страница 7: ...Designer Plus About This Guide This guide provides all the information needed to configure and use the Carbon Cortex M3 Model in Carbon SoC Designer Plus Audience This guide is intended for experienc...

Страница 8: ...nary text sparseMem_t SparseMemCreate New italic New or unusual words or phrases appearing for the first time Transactors provide the entry and exit points for data bold Action that the user per forms...

Страница 9: ...Designer Plus AHBv2 Protocol Bundle User Guide External publications The following publications provide reference information about ARM products Cortex M3 Technical Reference Manual AMBA 3 AHB Lite O...

Страница 10: ...Simulation Interface is based on the SystemC communication library and manages the interconnection of components and communication between components CADI ESL API Debug Interface enables reading and...

Страница 11: ...power processor that features low gate count low inter rupt latency and low cost debug It is intended for deeply embedded applications that require fast interrupt response features The processor impl...

Страница 12: ...ted in the Cortex M3 model but the exact behavior of the hardware implementation is not accurately repro duced because some approximations and optimizations have been made for simulation performance R...

Страница 13: ...use the semihost component from Carbon This CarbonSemihost component is included in the Carbon SoC Designer Plus Standard Model Library version 3 0 or greater The ARM RVML semihost component will not...

Страница 14: ...the SoC Designer Plus Component The following topics briefly describe how to use the component See the Carbon SoC Designer Plus User Guide for more information Carbon SoC Designer Plus Component Files...

Страница 15: ...ow click Add 5 Browse to the location where the SoC Designer Plus model is located and select the component configuration file maxlib lib model_name conf for Linux maxlib lib model_name windows conf f...

Страница 16: ...iption Direction Type AUXFAULT Auxiliary fault status information It is the input to AFSR Auxiliary Fault Status Register in NVIC where value fault number 0 31 Input Signal slave BIGEND This port indi...

Страница 17: ...current execution context Output Signal master ETMINTSTAT Interrupt status of the current cycle 000 no status 001 interrupt entry 010 interrupt exit 011 interrupt return 100 vector fetch and stack pu...

Страница 18: ...aster Port The ext_ppb bus master port implements the APB v3 0 interface on the Cortex M3 for accessing peripherals mapped in the external Private Peripheral Bus PPB region Data accesses to an address...

Страница 19: ...t Parameters You can change the settings of all the component parameters in SoC Designer Canvas and of some of the parameters in SoC Designer Simulator To modify the Carbon component s parameters 1 In...

Страница 20: ...e it disallows transac tions on the I and D interfaces at the same time true false false Yes Dump Waveforms Determines whether SoC Designer Plus dumps waveforms for this component true false false Yes...

Страница 21: ...es whether debug messages are logged for the mem_S port true false false Yes PC Tracing File When Enable PC Tracing is enabled this is the file in which the PC trace information is written The data is...

Страница 22: ...ator by right clicking on the model and choosing the appropriate menu entry Register Information Run To Debug Point Feature Memory Information Disassembly View 1 5 1 Register Information Figure 1 3 sh...

Страница 23: ...R4 R4 register read write 1 R5 R5 register read write 1 R6 R6 register read write 1 R7 R7 register read write 1 R8 R8 register read write 1 R9 R9 register read write 1 R10 R10 register read write 1 R...

Страница 24: ...xE000E108 read write write does a set enable SetEnable96_127 1 Set Enable96_127 register 0xE000E10C read write write does a set enable SetEnable128_159 1 Set Enable128_159 register 0xE000E110 read wri...

Страница 25: ...Pend224_239 1 Set Pend224_239 register 0xE000E21C read write write does a set pend ClearPend0_31 Clear Pend0_31 register 0xE000E280 read write write does a clear pend ClearPend32_63 1 Clear Pend32_63...

Страница 26: ...read write ConfigCtrl Config Control register 0xE000ED14 read write SysHandlerPri4_7 System Handlers 4 7 Priority register read write SysHandlerPri8_11 System Handlers 8 11 Priority register read writ...

Страница 27: ...e3 ISA Feature 3 register 0xE000ED6C read only ISAFeature4 ISA Feature 4 register 0xE000ED70 read only Nvic_PERIPHID 0 7 Nvic_PERIPHID 0 through 7 registers read only Nvic_PCELLID 0 3 Nvic_PCELLID 0 t...

Страница 28: ..._CYCCNT DWT_CYCCNT register read write DWT_CPICNT DWT_CPICNT register read write DWT_EXECNT DWT_EXECNT register read write DWT_SLEEPCNT DWT_SLEEPCNT register read write DWT_LSUCNT DWT_LSUCNT register...

Страница 29: ...is hit including single stepping However if a hardware breakpoint is reached or the system is advanced by cycles within SoC Designer Plus the model can get to a non debuggable state In this event the...

Страница 30: ...program running on the Cortex M3 model in SoC Designer Simulator To display the disassembly view in the SoC Designer Simulator right click on the Cortex M3 model and select View Disassembly from the...

Страница 31: ...ng includes just the Core Events stream The buckets supported by this stream are shown in Table 1 10 An example of debug information for the Core Events stream is shown below Figure 1 6 Software Strea...

Страница 32: ...1 22 Using the Model Kit Component in SoC Designer Plus Carbon Design Systems Inc Confidential...

Страница 33: ...ons and the following disclaimer in the documentation and or other materials provided with the distribution THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WA...

Страница 34: ...Carbon Design Systems Inc Confidential...

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