Campbell CR7, Инструкция по эксплуатации, Страница: 127 / 186

SECTION 13. CR7 MEASUREMENTS
13-3
13.3 THE EFFECT OF SENSOR LEAD
LENGTH ON THE SIGNAL SETTLING
TIME
Whenever an analog input is switched into the
CR7 measurement circuitry prior to making a
measurement, a finite amount of time is
required for the signal to stabilize at it's correct
value. The rate at which the signal settles is
determined by the input settling time constant
which is a function of both the source resistance
and input capacitance (explained below). The
CR7 allows a 0.5ms settling time before
initiating the measurement. In most
applications, this settling time is adequate but
the additional wire capacitance associated with
long sensor leads can increase the settling time
constant to the point that measurement errors
may occur. There are three potential sources of
error which must settle before the measurement
is made:
1. The signal must rise to its correct value.
2. A small transient (5mV) caused by
switching the analog input into the
measurement circuitry must settle.
3. A larger transient, usually about 40 mV/V,
caused by the switched, precision excitation
voltage used in resistive bridge
measurements must settle.
The purpose of this section is to bring attention
to potential measurement errors caused when
the input settling time constant gets too large
and discuss procedures whereby the effects of
lead length on the measurement can be
estimated. In addition, physical values are
given for three types of wire used in Campbell
Scientific sensors and error estimates for given
lead lengths are provided. Finally, techniques
are discussed for minimizing input settling error
when long leads are mandatory.
13.3.1 THE INPUT SETTLING TIME CONSTANT
The rate at which an input voltage rises to its full
value or that a transient decays to the correct
input level are both determined by the input
settling time constant. In both cases the
waveform is an exponential. Figure 13.3-1
shows both a rising and decaying waveform
settling to the signal level, Vso. The rising input
voltage is described by Equation 13.3-1 and the
decaying input voltage by Equation 13.3-2,
FIGURE 13.3-1. Input Voltage Rise and
Transient Decay
V V e
s so
t C
o T
= −
−
( )
/R
1 , rise [13.3-1]
V V V V e
s so eo so
t C
o T
= + −
−
( )
/R
, decay [13.3-2]
where Vs is the input voltage, Vso the true
signal voltage, Veo the peak transient voltage, t
is time in seconds, Ro the source resistance in
ohms and CT is the total capacitance between
the signal lead and ground (or some other fixed
reference value) in farads.
The settling time constant,
τ
in seconds, and the
capacitance relationships are given in
Equations 13.3-3 through 13.3-5,
τ
= RoCT [13.3-3]
CT = Cf + CwL [13.3-4]
Cf = 0.01 nfd [13.3-5]
where Cf is the fixed CR7 input capacitance in
farads, Cw is the wire capacitance in farads/foot
and L is the wire length in feet.
Equations 13.3-1 and 13.3-2 can be used to
estimate the input settling error, Ve, directly.
For the rising case, Vs = Vso-Ve whereas for
the decaying transient Vs = Vso+Ve.
Substituting these relationships for Vs in
Equations 13.3-1 and 13.3-2, respectively,
yields expressions in Ve, the input settling error:
V V e
e so
t C
o T
=
−
/R
, rise [13.3-6]
V V e
e eo
t C
o T
=
−
'
/R
, decay [13.3-7]
Where V'eo = Veo-Vso, the difference between
the peak transient voltage and the true signal
voltage.